| /llvm-project/llvm/include/llvm/IR/ |
| H A D | InlineAsm.h | 315 unsigned getRegClass() const { return Bitfield::get<RegClass>(Storage); } in getRegClass() function
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| /llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 103 static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) { in getRegClass() function
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| /llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 172 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { getRegClass() function in X86InstructionSelector
202 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, getRegClass() function in X86InstructionSelector
[all...] |
| /llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 451 const MCRegisterClass& getRegClass(unsigned i) const { getRegClass() function
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 653 const TargetRegisterClass *getRegClass(Register Reg) const { getRegClass() function
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| H A D | TargetRegisterInfo.h | 818 const TargetRegisterClass *getRegClass(unsigned i) const { getRegClass() function
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| /llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 116 const TargetRegisterClass *getRegClass() const { getRegClass() function
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 48 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() function in TargetInstrInfo
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| /llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 1380 CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const { in getRegClass() function in CodeGenRegBank
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 3141 SIRegisterInfo::getRegClass(unsigned RCID) const { getRegClass() function in SIRegisterInfo
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| H A D | SIInstrInfo.cpp | 5582 const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID, getRegClass() function in SIInstrInfo
[all...] |
| /llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 301 PerTargetMIParsingState::getRegClass(StringRef Name) { getRegClass() function in PerTargetMIParsingState
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4129 static const TargetRegisterClass *getRegClass(const MachineInstr &MI, getRegClass() function
5572 auto getRegClass = [&](unsigned Reg) { foldMemoryOperandImpl() local
[all...] |
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 94 X86InstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, getRegClass() function in X86InstrInfo
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2493 static int getRegClass(RegisterKind Is, unsigned RegWidth) { getRegClass() function
[all...] |