SIInstrInfo.cpp - OpenGrok cross reference for /llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines Matching defs:getRegClass
201         RI.isSGPRClass(MRI.getRegClass(Op.getReg()))) {
1178   const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
1242   assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
2599         RI.getAllocatableClass(getRegClass(TID, 0, &RI, *MF));
2774       OpInfo1.RegClass != -1 ? RI.getRegClass(OpInfo1.RegClass) : nullptr;
2776       OpInfo1.RegClass != -1 ? RI.getRegClass(OpInfo0.RegClass) : nullptr;
3272     const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
3273     if (MRI.getRegClass(FalseReg) != RC)
3287     const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
3288     if (MRI.getRegClass(FalseReg) != RC)
3316   const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
3534         !RI.getRegClass(NewMCID.operands()[0].RegClass)->contains(DstReg))
3578       if (RI.isSGPRClass(MRI->getRegClass(RegSrc->getReg())) &&
3582       if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
4638     return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
4882       const TargetRegisterClass *RC = RI.getRegClass(RegClass);
5415       const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
5739   return RI.getProperlyAlignedRC(RI.getRegClass(RCID));
5742 const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,
5781       return MRI.getRegClass(Reg);
5795   const TargetRegisterClass *RC = RI.getRegClass(RCID);
5863   const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
5867   const TargetRegisterClass *RC = MRI.getRegClass(Reg);
5943       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
6156     if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
6162     if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) {
6234   const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
6285   if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) {
6385   if (!SAddr || RI.isSGPRClass(MRI.getRegClass(SAddr->getReg())))
6391   const TargetRegisterClass *DeclaredRC = getRegClass(
6548           TRI->getEquivalentSGPRClass(MRI.getRegClass(VScalarOp));
6775           MRI.getRegClass(MI.getOperand(i).getReg());
6836         const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
6854     const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
6855     const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
6867     if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg())))
6881     if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg())))
6896     if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg())))
6901     if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg())))
6910     if (!RI.isSGPRClass(MRI.getRegClass(Dest->getReg()))) {
6955         !RI.isSGPRClass(MRI.getRegClass(Soffset->getReg()))) {
7388         MRI.getRegClass(Inst.getOperand(0).getReg())));
7414         RI.getEquivalentVGPRClass(MRI.getRegClass(Dest0.getReg()));
7836       RI.getEquivalentVGPRClass(MRI.getRegClass(Dest.getReg())));
7912                       RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
7914                       RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));
8021     MRI.getRegClass(Src0.getReg()) :
8030   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
8084   const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
8085   const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
8193   const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
8194   const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
8255     MRI.getRegClass(Src0.getReg()) :
8261     MRI.getRegClass(Src1.getReg()) :
8276   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
8320   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
8362     MRI.getRegClass(Src.getReg()) :
8471       Src.isReg() ? MRI.getRegClass(Src.getReg()) : &AMDGPU::SGPR_32RegClass;
8756         RI.getRegClass(Desc.operands()[Idx].RegClass);
8763     const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
9199   return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass);
9713       const TargetRegisterClass *RC = MRI.getRegClass(VirtReg);