| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_rq_dlg_calc_32.c | 215 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml32_rq_dlg_get_dlg_reg() local
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 538 display_clocks_and_cfg_st *clks = &pipes[j].clks_cfg; in fetch_pipe_params() local
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| /openbsd-src/sys/dev/pci/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_pp_smu.c | 112 struct dm_pp_clock_levels *clks) in get_default_clock_levels()
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| H A D | amdgpu_dm_helpers.c | 979 dm_set_dcn_clocks(struct dc_context * ctx,struct dc_clocks * clks) dm_set_dcn_clocks() argument
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| /openbsd-src/sys/dev/pci/drm/amd/pm/swsmu/smu12/ |
| H A D | renoir_ppt.c | 699 enum smu_clk_type clks[] = { in renoir_force_dpm_limit_value() enum
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dce112/ |
| H A D | dce112_resource.c | 1069 struct dm_pp_clock_levels clks = {0}; in bw_calcs_data_update_from_pplib() local
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dce110/ |
| H A D | dce110_resource.c | 1285 struct dm_pp_clock_levels clks = {0}; in bw_calcs_data_update_from_pplib() local
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_rq_dlg_calc_30.c | 909 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params() local
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_rq_dlg_calc_20v2.c | 798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params() local
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| H A D | display_rq_dlg_calc_20.c | 798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params() local
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_rq_dlg_calc_31.c | 869 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params() local
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_resource.c | 1291 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) in verify_clock_values()
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_rq_dlg_calc_314.c | 954 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params() local
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_rq_dlg_calc_21.c | 844 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params() local
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 306 struct dc_clocks clks; member
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| /openbsd-src/sys/dev/pci/drm/amd/pm/swsmu/smu11/ |
| H A D | vangogh_ppt.c | 1317 enum smu_clk_type clks[] = { vangogh_force_dpm_limit_value() enum
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| /openbsd-src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu8_hwmgr.c | 760 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; smu8_set_deep_sleep_sclk_threshold() local
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| /openbsd-src/sys/dev/pci/drm/amd/pm/powerplay/smumgr/ |
| H A D | iceland_smumgr.c | 1132 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; in iceland_calculate_mclk_params() local
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| H A D | tonga_smumgr.c | 884 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; in tonga_calculate_mclk_params() local
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| H A D | ci_smumgr.c | 1087 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; in ci_calculate_mclk_params() local
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| /openbsd-src/sys/dev/pci/drm/radeon/ |
| H A D | ci_dpm.c | 2803 u32 clks = reference_clock * 5 / ss.rate; in ci_calculate_mclk_params() local
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| H A D | si_dpm.c | 4910 u32 clks = reference_clock * 5 / ss.rate; in si_populate_mclk_value() local
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| /openbsd-src/sys/dev/pci/drm/amd/pm/legacy-dpm/ |
| H A D | amdgpu_si_dpm.c | 5412 u32 clks = reference_clock * 5 / ss.rate; in si_populate_mclk_value() local
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