1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
3 * All rights reserved.
4 */
5
6 /* This file should not be included directly. Include common.h instead. */
7
8 #ifndef __T4_ADAPTER_H__
9 #define __T4_ADAPTER_H__
10
11 #include <bus_pci_driver.h>
12 #include <rte_mbuf.h>
13 #include <rte_io.h>
14 #include <rte_rwlock.h>
15 #include <ethdev_driver.h>
16
17 #include "../cxgbe_compat.h"
18 #include "../cxgbe_ofld.h"
19 #include "t4_regs_values.h"
20
21 enum {
22 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
23 };
24
25 struct adapter;
26 struct sge_rspq;
27
28 enum {
29 PORT_RSS_DONE = (1 << 0),
30 };
31
32 struct port_info {
33 struct adapter *adapter; /* adapter that this port belongs to */
34 struct rte_eth_dev *eth_dev; /* associated rte eth device */
35 struct port_stats stats_base; /* port statistics base */
36 struct link_config link_cfg; /* link configuration info */
37
38 unsigned long flags; /* port related flags */
39 short int xact_addr_filt; /* index of exact MAC address filter */
40
41 u16 viid; /* associated virtual interface id */
42 u8 port_id; /* physical port ID */
43 u8 pidx; /* port index for this PF */
44 u8 tx_chan; /* associated channel */
45
46 u16 n_rx_qsets; /* # of rx qsets */
47 u16 n_tx_qsets; /* # of tx qsets */
48 u16 first_rxqset; /* index of first rxqset */
49 u16 first_txqset; /* index of first txqset */
50
51 u16 *rss; /* rss table */
52 u8 rss_mode; /* rss mode */
53 u16 rss_size; /* size of VI's RSS table slice */
54 u64 rss_hf; /* RSS Hash Function */
55
56 /* viid fields either returned by fw
57 * or decoded by parsing viid by driver.
58 */
59 u8 vin;
60 u8 vivld;
61
62 u8 vi_en_rx; /* Enable/disable VI Rx */
63 u8 vi_en_tx; /* Enable/disable VI Tx */
64 };
65
66 enum { /* adapter flags */
67 FULL_INIT_DONE = (1 << 0),
68 USING_MSI = (1 << 1),
69 USING_MSIX = (1 << 2),
70 FW_QUEUE_BOUND = (1 << 3),
71 FW_OK = (1 << 4),
72 CFG_QUEUES = (1 << 5),
73 MASTER_PF = (1 << 6),
74 };
75
76 struct rx_sw_desc { /* SW state per Rx descriptor */
77 void *buf; /* struct page or mbuf */
78 dma_addr_t dma_addr;
79 };
80
81 struct sge_fl { /* SGE free-buffer queue state */
82 /* RO fields */
83 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
84
85 dma_addr_t addr; /* bus address of HW ring start */
86 __be64 *desc; /* address of HW Rx descriptor ring */
87
88 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
89 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
90
91 unsigned int cntxt_id; /* SGE relative QID for the free list */
92 unsigned int size; /* capacity of free list */
93
94 unsigned int avail; /* # of available Rx buffers */
95 unsigned int pend_cred; /* new buffers since last FL DB ring */
96 unsigned int cidx; /* consumer index */
97 unsigned int pidx; /* producer index */
98
99 unsigned long alloc_failed; /* # of times buffer allocation failed */
100 unsigned long low; /* # of times momentarily starving */
101 u8 fl_buf_size_idx; /* Selected SGE_FL_BUFFER_SIZE index */
102 };
103
104 #define MAX_MBUF_FRAGS (16384 / 512 + 2)
105
106 /* A packet gather list */
107 struct pkt_gl {
108 union {
109 struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
110 } /* UNNAMED */;
111 void *va; /* virtual address of first byte */
112 unsigned int nfrags; /* # of fragments */
113 unsigned int tot_len; /* total length of fragments */
114 };
115
116 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
117 const struct pkt_gl *gl);
118
119 struct sge_rspq { /* state for an SGE response queue */
120 struct adapter *adapter; /* adapter that this queue belongs to */
121 struct rte_eth_dev *eth_dev; /* associated rte eth device */
122 struct rte_mempool *mb_pool; /* associated mempool */
123
124 dma_addr_t phys_addr; /* physical address of the ring */
125 __be64 *desc; /* address of HW response ring */
126 const __be64 *cur_desc; /* current descriptor in queue */
127
128 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
129 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
130 struct sge_qstat *stat;
131
132 unsigned int cidx; /* consumer index */
133 unsigned int gts_idx; /* last gts write sent */
134 unsigned int iqe_len; /* entry size */
135 unsigned int size; /* capacity of response queue */
136 int offset; /* offset into current Rx buffer */
137
138 u8 gen; /* current generation bit */
139 u8 intr_params; /* interrupt holdoff parameters */
140 u8 next_intr_params; /* holdoff params for next interrupt */
141 u8 pktcnt_idx; /* interrupt packet threshold */
142 u8 port_id; /* associated port-id */
143 u8 idx; /* queue index within its group */
144 u16 cntxt_id; /* SGE relative QID for the response Q */
145 u16 abs_id; /* absolute SGE id for the response q */
146
147 rspq_handler_t handler; /* associated handler for this response q */
148 };
149
150 struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
151 u64 pkts; /* # of ethernet packets */
152 u64 rx_bytes; /* # of ethernet bytes */
153 u64 rx_cso; /* # of Rx checksum offloads */
154 u64 vlan_ex; /* # of Rx VLAN extractions */
155 u64 rx_drops; /* # of packets dropped due to no mem */
156 };
157
158 struct __rte_cache_aligned sge_eth_rxq { /* a SW Ethernet Rx queue */
159 unsigned int flags; /* flags for state of the queue */
160 struct sge_rspq rspq;
161 struct sge_fl fl;
162 struct sge_eth_rx_stats stats;
163 };
164
165 /*
166 * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
167 * packet (if one sgl is present) and type 1 needs 32 bytes. This means
168 * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
169 * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
170 * to be able to free those mbufs when we get completions back from the FW.
171 * Allocating the maximum number of pointers in every tx desc is a waste
172 * of memory resources so we only store 2 pointers per tx desc which should
173 * be enough since a tx desc can only fit 2 packets in the best case
174 * scenario where a packet needs 32 bytes.
175 */
176 #define ETH_COALESCE_PKT_NUM 15
177 #define ETH_COALESCE_VF_PKT_NUM 7
178 #define ETH_COALESCE_PKT_PER_DESC 2
179
180 struct tx_eth_coal_desc {
181 struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
182 struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
183 int idx;
184 };
185
186 struct tx_desc {
187 __be64 flit[8];
188 };
189
190 struct tx_sw_desc { /* SW state per Tx descriptor */
191 struct rte_mbuf *mbuf;
192 struct ulptx_sgl *sgl;
193 struct tx_eth_coal_desc coalesce;
194 };
195
196 enum cxgbe_txq_state {
197 EQ_STOPPED = (1 << 0),
198 };
199
200 enum cxgbe_rxq_state {
201 IQ_STOPPED = (1 << 0),
202 };
203
204 struct eth_coalesce {
205 unsigned char *ptr;
206 unsigned char type;
207 unsigned int idx;
208 unsigned int len;
209 unsigned int flits;
210 unsigned int max;
211 __u8 ethmacdst[ETHER_ADDR_LEN];
212 __u8 ethmacsrc[ETHER_ADDR_LEN];
213 __be16 ethtype;
214 __be16 vlantci;
215 };
216
217 struct sge_txq {
218 struct tx_desc *desc; /* address of HW Tx descriptor ring */
219 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
220 struct sge_qstat *stat; /* queue status entry */
221 struct eth_coalesce coalesce; /* coalesce info */
222
223 uint64_t phys_addr; /* physical address of the ring */
224
225 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
226 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
227
228 unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
229 unsigned int in_use; /* # of in-use Tx descriptors */
230 unsigned int size; /* # of descriptors */
231 unsigned int cidx; /* SW consumer index */
232 unsigned int pidx; /* producer index */
233 unsigned int dbidx; /* last idx when db ring was done */
234 unsigned int equeidx; /* last sent credit request */
235 unsigned int last_pidx; /* last pidx recorded by tx monitor */
236 unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
237 unsigned int abs_id;
238
239 int db_disabled; /* doorbell state */
240 unsigned short db_pidx; /* doorbell producer index */
241 unsigned short db_pidx_inc; /* doorbell producer increment */
242 };
243
244 struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
245 u64 pkts; /* # of ethernet packets */
246 u64 tx_bytes; /* # of ethernet bytes */
247 u64 tso; /* # of TSO requests */
248 u64 tx_cso; /* # of Tx checksum offloads */
249 u64 vlan_ins; /* # of Tx VLAN insertions */
250 u64 mapping_err; /* # of I/O MMU packet mapping errors */
251 u64 coal_wr; /* # of coalesced wr */
252 u64 coal_pkts; /* # of coalesced packets */
253 };
254
255 struct __rte_cache_aligned sge_eth_txq { /* state for an SGE Ethernet Tx queue */
256 struct sge_txq q;
257 struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
258 struct rte_eth_dev_data *data;
259 struct sge_eth_tx_stats stats; /* queue statistics */
260 rte_spinlock_t txq_lock;
261
262 unsigned int flags; /* flags for state of the queue */
263 };
264
265 struct __rte_cache_aligned sge_ctrl_txq { /* State for an SGE control Tx queue */
266 struct sge_txq q; /* txq */
267 struct adapter *adapter; /* adapter associated with this queue */
268 rte_spinlock_t ctrlq_lock; /* control queue lock */
269 u8 full; /* the Tx ring is full */
270 u64 txp; /* number of transmits */
271 struct rte_mempool *mb_pool; /* mempool to generate ctrl pkts */
272 };
273
274 struct sge {
275 struct sge_eth_txq *ethtxq;
276 struct sge_eth_rxq *ethrxq;
277 alignas(RTE_CACHE_LINE_SIZE) struct sge_rspq fw_evtq;
278 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
279
280 u16 max_ethqsets; /* # of available Ethernet queue sets */
281 u32 stat_len; /* length of status page at ring end */
282 u32 pktshift; /* padding between CPL & packet data */
283
284 /* response queue interrupt parameters */
285 u16 timer_val[SGE_NTIMERS];
286 u8 counter_val[SGE_NCOUNTERS];
287
288 u32 fl_starve_thres; /* Free List starvation threshold */
289 u32 fl_buffer_size[SGE_FL_BUFFER_SIZE_NUM]; /* Free List buffer sizes */
290 };
291
292 /*
293 * OS Lock/List primitives for those interfaces in the Common Code which
294 * need this.
295 */
296
297 struct mbox_entry {
298 TAILQ_ENTRY(mbox_entry) next;
299 };
300
301 TAILQ_HEAD(mbox_list, mbox_entry);
302
303 struct adapter_devargs {
304 bool keep_ovlan;
305 bool force_link_up;
306 bool tx_mode_latency;
307 u32 filtermode;
308 u32 filtermask;
309 };
310
311 struct adapter {
312 struct rte_pci_device *pdev; /* associated rte pci device */
313 struct rte_eth_dev *eth_dev; /* first port's rte eth device */
314 struct adapter_params params; /* adapter parameters */
315 struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */
316 struct sge sge; /* associated SGE */
317
318 /* support for single-threading access to adapter mailbox registers */
319 struct mbox_list mbox_list;
320 rte_spinlock_t mbox_lock;
321
322 u8 *regs; /* pointer to registers region */
323 u8 *bar2; /* pointer to bar2 region */
324 unsigned long flags; /* adapter flags */
325 unsigned int mbox; /* associated mailbox */
326 unsigned int pf; /* associated physical function id */
327
328 unsigned int vpd_busy;
329 unsigned int vpd_flag;
330
331 int use_unpacked_mode; /* unpacked rx mode state */
332 rte_spinlock_t win0_lock;
333
334 rte_spinlock_t flow_lock; /* Serialize access for rte_flow ops */
335
336 unsigned int clipt_start; /* CLIP table start */
337 unsigned int clipt_end; /* CLIP table end */
338 unsigned int l2t_start; /* Layer 2 table start */
339 unsigned int l2t_end; /* Layer 2 table end */
340 struct clip_tbl *clipt; /* CLIP table */
341 struct l2t_data *l2t; /* Layer 2 table */
342 struct smt_data *smt; /* Source mac table */
343 struct mpstcam_table *mpstcam;
344
345 struct tid_info tids; /* Info used to access TID related tables */
346
347 struct adapter_devargs devargs;
348 };
349
350 /**
351 * t4_os_rwlock_init - initialize rwlock
352 * @lock: the rwlock
353 */
354 #define t4_os_rwlock_init(lock) rte_rwlock_init(lock)
355
356 /**
357 * t4_os_write_lock - get a write lock
358 * @lock: the rwlock
359 */
360 #define t4_os_write_lock(lock) rte_rwlock_write_lock(lock)
361
362 /**
363 * t4_os_write_unlock - unlock a write lock
364 * @lock: the rwlock
365 */
366 #define t4_os_write_unlock(lock) rte_rwlock_write_unlock(lock)
367
368 /**
369 * ethdev2pinfo - return the port_info structure associated with a rte_eth_dev
370 * @dev: the rte_eth_dev
371 *
372 * Return the struct port_info associated with a rte_eth_dev
373 */
ethdev2pinfo(const struct rte_eth_dev * dev)374 static inline struct port_info *ethdev2pinfo(const struct rte_eth_dev *dev)
375 {
376 return dev->data->dev_private;
377 }
378
379 /**
380 * adap2pinfo - return the port_info of a port
381 * @adap: the adapter
382 * @idx: the port index
383 *
384 * Return the port_info structure for the port of the given index.
385 */
adap2pinfo(const struct adapter * adap,int idx)386 static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx)
387 {
388 return adap->port[idx];
389 }
390
391 /**
392 * ethdev2adap - return the adapter structure associated with a rte_eth_dev
393 * @dev: the rte_eth_dev
394 *
395 * Return the struct adapter associated with a rte_eth_dev
396 */
ethdev2adap(const struct rte_eth_dev * dev)397 static inline struct adapter *ethdev2adap(const struct rte_eth_dev *dev)
398 {
399 return ethdev2pinfo(dev)->adapter;
400 }
401
402 #define CXGBE_PCI_REG(reg) rte_read32(reg)
403
cxgbe_read_addr64(volatile void * addr)404 static inline uint64_t cxgbe_read_addr64(volatile void *addr)
405 {
406 uint64_t val = CXGBE_PCI_REG(addr);
407 uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
408
409 val2 = (uint64_t)(val2 << 32);
410 val += val2;
411 return val;
412 }
413
cxgbe_read_addr(volatile void * addr)414 static inline uint32_t cxgbe_read_addr(volatile void *addr)
415 {
416 return CXGBE_PCI_REG(addr);
417 }
418
419 #define CXGBE_PCI_REG_ADDR(adap, reg) \
420 ((volatile uint32_t *)((char *)(adap)->regs + (reg)))
421
422 #define CXGBE_READ_REG(adap, reg) \
423 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
424
425 #define CXGBE_READ_REG64(adap, reg) \
426 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
427
428 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
429
430 #define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
431 rte_write32_relaxed((value), (reg))
432
433 #define CXGBE_WRITE_REG(adap, reg, value) \
434 CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
435
436 #define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \
437 CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
438
cxgbe_write_addr64(volatile void * addr,uint64_t val)439 static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
440 {
441 CXGBE_PCI_REG_WRITE(addr, val);
442 CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
443 return val;
444 }
445
446 #define CXGBE_WRITE_REG64(adap, reg, value) \
447 cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
448
449 /**
450 * t4_read_reg - read a HW register
451 * @adapter: the adapter
452 * @reg_addr: the register address
453 *
454 * Returns the 32-bit value of the given HW register.
455 */
t4_read_reg(struct adapter * adapter,u32 reg_addr)456 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
457 {
458 return CXGBE_READ_REG(adapter, reg_addr);
459 }
460
461 /**
462 * t4_write_reg - write a HW register with barrier
463 * @adapter: the adapter
464 * @reg_addr: the register address
465 * @val: the value to write
466 *
467 * Write a 32-bit value into the given HW register.
468 */
t4_write_reg(struct adapter * adapter,u32 reg_addr,u32 val)469 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
470 {
471 CXGBE_WRITE_REG(adapter, reg_addr, val);
472 }
473
474 /**
475 * t4_write_reg_relaxed - write a HW register with no barrier
476 * @adapter: the adapter
477 * @reg_addr: the register address
478 * @val: the value to write
479 *
480 * Write a 32-bit value into the given HW register.
481 */
t4_write_reg_relaxed(struct adapter * adapter,u32 reg_addr,u32 val)482 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr,
483 u32 val)
484 {
485 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val);
486 }
487
488 /**
489 * t4_read_reg64 - read a 64-bit HW register
490 * @adapter: the adapter
491 * @reg_addr: the register address
492 *
493 * Returns the 64-bit value of the given HW register.
494 */
t4_read_reg64(struct adapter * adapter,u32 reg_addr)495 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
496 {
497 return CXGBE_READ_REG64(adapter, reg_addr);
498 }
499
500 /**
501 * t4_write_reg64 - write a 64-bit HW register
502 * @adapter: the adapter
503 * @reg_addr: the register address
504 * @val: the value to write
505 *
506 * Write a 64-bit value into the given HW register.
507 */
t4_write_reg64(struct adapter * adapter,u32 reg_addr,u64 val)508 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
509 u64 val)
510 {
511 CXGBE_WRITE_REG64(adapter, reg_addr, val);
512 }
513
514 #define PCI_CAP_ID_EXP RTE_PCI_CAP_ID_EXP
515 #define PCI_EXP_DEVCTL 0x0008 /* Device control */
516 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
517 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
518 #define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
519 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
520 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
521 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
522 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
523
524 /**
525 * t4_os_pci_write_cfg4 - 32-bit write to PCI config space
526 * @adapter: the adapter
527 * @addr: the register address
528 * @val: the value to write
529 *
530 * Write a 32-bit value into the given register in PCI config space.
531 */
t4_os_pci_write_cfg4(struct adapter * adapter,size_t addr,off_t val)532 static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr,
533 off_t val)
534 {
535 u32 val32 = val;
536
537 if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
538 addr) < 0)
539 dev_err(adapter, "Can't write to PCI config space\n");
540 }
541
542 /**
543 * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space
544 * @adapter: the adapter
545 * @addr: the register address
546 * @val: where to store the value read
547 *
548 * Read a 32-bit value from the given register in PCI config space.
549 */
t4_os_pci_read_cfg4(struct adapter * adapter,size_t addr,u32 * val)550 static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
551 u32 *val)
552 {
553 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
554 addr) < 0)
555 dev_err(adapter, "Can't read from PCI config space\n");
556 }
557
558 /**
559 * t4_os_pci_write_cfg2 - 16-bit write to PCI config space
560 * @adapter: the adapter
561 * @addr: the register address
562 * @val: the value to write
563 *
564 * Write a 16-bit value into the given register in PCI config space.
565 */
t4_os_pci_write_cfg2(struct adapter * adapter,size_t addr,off_t val)566 static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr,
567 off_t val)
568 {
569 u16 val16 = val;
570
571 if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
572 addr) < 0)
573 dev_err(adapter, "Can't write to PCI config space\n");
574 }
575
576 /**
577 * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space
578 * @adapter: the adapter
579 * @addr: the register address
580 * @val: where to store the value read
581 *
582 * Read a 16-bit value from the given register in PCI config space.
583 */
t4_os_pci_read_cfg2(struct adapter * adapter,size_t addr,u16 * val)584 static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
585 u16 *val)
586 {
587 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
588 addr) < 0)
589 dev_err(adapter, "Can't read from PCI config space\n");
590 }
591
592 /**
593 * t4_os_pci_read_cfg - read a 8-bit value from PCI config space
594 * @adapter: the adapter
595 * @addr: the register address
596 * @val: where to store the value read
597 *
598 * Read a 8-bit value from the given register in PCI config space.
599 */
t4_os_pci_read_cfg(struct adapter * adapter,size_t addr,u8 * val)600 static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
601 u8 *val)
602 {
603 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
604 addr) < 0)
605 dev_err(adapter, "Can't read from PCI config space\n");
606 }
607
608 /**
609 * t4_os_find_pci_capability - lookup a capability in the PCI capability list
610 * @adapter: the adapter
611 * @cap: the capability
612 *
613 * Return the address of the given capability within the PCI capability list.
614 */
t4_os_find_pci_capability(struct adapter * adapter,int cap)615 static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
616 {
617 if (!rte_pci_has_capability_list(adapter->pdev)) {
618 dev_err(adapter, "PCIe capability reading failed\n");
619 return -1;
620 }
621
622 return rte_pci_find_capability(adapter->pdev, cap);
623 }
624
625 /**
626 * t4_os_set_hw_addr - store a port's MAC address in SW
627 * @adapter: the adapter
628 * @port_idx: the port index
629 * @hw_addr: the Ethernet address
630 *
631 * Store the Ethernet address of the given port in SW. Called by the
632 * common code when it retrieves a port's Ethernet address from EEPROM.
633 */
t4_os_set_hw_addr(struct adapter * adapter,int port_idx,u8 hw_addr[])634 static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
635 u8 hw_addr[])
636 {
637 struct port_info *pi = adap2pinfo(adapter, port_idx);
638
639 rte_ether_addr_copy((struct rte_ether_addr *)hw_addr,
640 &pi->eth_dev->data->mac_addrs[0]);
641 }
642
643 /**
644 * t4_os_lock_init - initialize spinlock
645 * @lock: the spinlock
646 */
647 #define t4_os_lock_init(lock) rte_spinlock_init(lock)
648
649 /**
650 * t4_os_lock - spin until lock is acquired
651 * @lock: the spinlock
652 */
653 #define t4_os_lock(lock) rte_spinlock_lock(lock)
654
655 /**
656 * t4_os_unlock - unlock a spinlock
657 * @lock: the spinlock
658 */
659 #define t4_os_unlock(lock) rte_spinlock_unlock(lock)
660
661 /**
662 * t4_os_trylock - try to get a lock
663 * @lock: the spinlock
664 */
665 #define t4_os_trylock(lock) rte_spinlock_trylock(lock)
666
667 /**
668 * t4_os_init_list_head - initialize
669 * @head: head of list to initialize [to empty]
670 */
t4_os_init_list_head(struct mbox_list * head)671 static inline void t4_os_init_list_head(struct mbox_list *head)
672 {
673 TAILQ_INIT(head);
674 }
675
t4_os_list_first_entry(struct mbox_list * head)676 static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
677 {
678 return TAILQ_FIRST(head);
679 }
680
681 /**
682 * t4_os_atomic_add_tail - Enqueue list element atomically onto list
683 * @new: the entry to be addded to the queue
684 * @head: current head of the linked list
685 * @lock: lock to use to guarantee atomicity
686 */
t4_os_atomic_add_tail(struct mbox_entry * entry,struct mbox_list * head,rte_spinlock_t * lock)687 static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
688 struct mbox_list *head,
689 rte_spinlock_t *lock)
690 {
691 t4_os_lock(lock);
692 TAILQ_INSERT_TAIL(head, entry, next);
693 t4_os_unlock(lock);
694 }
695
696 /**
697 * t4_os_atomic_list_del - Dequeue list element atomically from list
698 * @entry: the entry to be remove/dequeued from the list.
699 * @lock: the spinlock
700 */
t4_os_atomic_list_del(struct mbox_entry * entry,struct mbox_list * head,rte_spinlock_t * lock)701 static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
702 struct mbox_list *head,
703 rte_spinlock_t *lock)
704 {
705 t4_os_lock(lock);
706 TAILQ_REMOVE(head, entry, next);
707 t4_os_unlock(lock);
708 }
709
710 /**
711 * t4_init_completion - initialize completion
712 * @c: the completion context
713 */
t4_init_completion(struct t4_completion * c)714 static inline void t4_init_completion(struct t4_completion *c)
715 {
716 c->done = 0;
717 t4_os_lock_init(&c->lock);
718 }
719
720 /**
721 * t4_complete - set completion as done
722 * @c: the completion context
723 */
t4_complete(struct t4_completion * c)724 static inline void t4_complete(struct t4_completion *c)
725 {
726 t4_os_lock(&c->lock);
727 c->done = 1;
728 t4_os_unlock(&c->lock);
729 }
730
731 /**
732 * cxgbe_port_viid - get the VI id of a port
733 * @dev: the device for the port
734 *
735 * Return the VI id of the given port.
736 */
cxgbe_port_viid(const struct rte_eth_dev * dev)737 static inline unsigned int cxgbe_port_viid(const struct rte_eth_dev *dev)
738 {
739 return ethdev2pinfo(dev)->viid;
740 }
741
742 void *t4_alloc_mem(size_t size);
743 void t4_free_mem(void *addr);
744 #define t4_os_alloc(_size) t4_alloc_mem((_size))
745 #define t4_os_free(_ptr) t4_free_mem((_ptr))
746
747 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
748 void t4_os_link_changed(struct adapter *adap, int port_id);
749
750 void reclaim_completed_tx(struct sge_txq *q);
751 void t4_free_sge_resources(struct adapter *adap);
752 void t4_sge_tx_monitor_start(struct adapter *adap);
753 void t4_sge_tx_monitor_stop(struct adapter *adap);
754 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
755 uint16_t nb_pkts);
756 int t4_mgmt_tx(struct sge_ctrl_txq *txq, struct rte_mbuf *mbuf);
757 int t4_sge_init(struct adapter *adap);
758 int t4vf_sge_init(struct adapter *adap);
759 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
760 struct rte_eth_dev *eth_dev, uint16_t queue_id,
761 unsigned int iqid, int socket_id);
762 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
763 struct rte_eth_dev *eth_dev, uint16_t queue_id,
764 unsigned int iqid, int socket_id);
765 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
766 struct rte_eth_dev *eth_dev, int intr_idx,
767 struct sge_fl *fl, rspq_handler_t handler,
768 int cong, struct rte_mempool *mp, int queue_id,
769 int socket_id);
770 int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
771 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
772 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
773 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_eth_rxq *rxq);
774 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_eth_rxq *rxq);
775 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
776 void t4_sge_eth_clear_queues(struct port_info *pi);
777 void t4_sge_eth_release_queues(struct port_info *pi);
778 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
779 unsigned int cnt);
780 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
781 unsigned int budget, unsigned int *work_done);
782 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues);
783 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t flags);
784
785 #endif /* __T4_ADAPTER_H__ */
786