drivers: move alignment attribute on types for MSVC

Move location of __rte_aligned(a) to new conventional location. The new
placement between {struct,union} and the tag allows the desired
alignment

drivers: move alignment attribute on types for MSVC

Move location of __rte_aligned(a) to new conventional location. The new
placement between {struct,union} and the tag allows the desired
alignment to be imparted on the type regardless of the toolchain being
used for both C and C++. Additionally, it avoids confusion by Doxygen
when generating documentation.

Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>

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pci: define some capability constants

Define some PCI capability constants and use them in existing drivers.

Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <br

pci: define some capability constants

Define some PCI capability constants and use them in existing drivers.

Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Chenbo Xia <chenbo.xia@intel.com>
Acked-by: Abdullah Sevincer <abdullah.sevincer@intel.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>

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bus/pci: find PCI capability

Introduce two helpers so that drivers stop reinventing the wheel when it
comes to finding capabilities in a device PCI configuration space.
Use it in existing drivers.

bus/pci: find PCI capability

Introduce two helpers so that drivers stop reinventing the wheel when it
comes to finding capabilities in a device PCI configuration space.
Use it in existing drivers.

Note:
- base/ drivers code is left untouched, only some wrappers in cxgbe
are touched,
- bnx2x maintained a per device cache of capabilities, this code has been
reworked to only cache the capabilities used in this driver,

Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
Reviewed-by: Chenbo Xia <chenbo.xia@intel.com>

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net/cxgbe: inherit lock annotations

Due to clang limitation, inline helpers don't inherit lock annotations
from the EAL lock API.
Replace them with macros.

Signed-off-by: David Marchand <david.marc

net/cxgbe: inherit lock annotations

Due to clang limitation, inline helpers don't inherit lock annotations
from the EAL lock API.
Replace them with macros.

Signed-off-by: David Marchand <david.marchand@redhat.com>

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bus/pci: make driver-only headers private

The pci bus interface is for drivers only.
Mark as internal and move the header in the driver headers list.

While at it, cleanup the code:
- fix indentatio

bus/pci: make driver-only headers private

The pci bus interface is for drivers only.
Mark as internal and move the header in the driver headers list.

While at it, cleanup the code:
- fix indentation,
- remove unneeded reference to bus specific singleton object,
- remove unneeded list head structure type,
- reorder the definitions and macro manipulating the bus singleton object,
- remove inclusion of rte_bus.h and fix the code that relied on implicit
inclusion,

Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>

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net/cxgbe: simplify Rx payload buffer size posting

Match the closest supported Rx payload buffer size with the mempool
data size and program it for the Rx queue. This removes unnecessary
need for ha

net/cxgbe: simplify Rx payload buffer size posting

Match the closest supported Rx payload buffer size with the mempool
data size and program it for the Rx queue. This removes unnecessary
need for handling additional padding, packing, and alignment, when
posting Rx buffers to hardware.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: fix dangling pointer by mailbox access rework

Rework mailbox access serialization to dynamically allocate and
free mbox entry. Also remove unnecessary temp memory and macros.

Observed wi

net/cxgbe: fix dangling pointer by mailbox access rework

Rework mailbox access serialization to dynamically allocate and
free mbox entry. Also remove unnecessary temp memory and macros.

Observed with: gcc-12.0 (GCC) 12.0.1 20220118 (experimental)

In file included from ../lib/eal/linux/include/rte_os.h:14,
from ../lib/eal/include/rte_common.h:28,
from ../lib/eal/include/rte_log.h:25,
from ../lib/ethdev/rte_ethdev.h:164,
from ../lib/ethdev/ethdev_driver.h:18,
from ../drivers/net/cxgbe/base/t4vf_hw.c:6:
In function ‘t4_os_atomic_add_tail’,
inlined from ‘t4vf_wr_mbox_core’ at
../drivers/net/cxgbe/base/t4vf_hw.c:115:2:
../drivers/net/cxgbe/base/adapter.h:742:9:
warning: storing the address of local variable ‘entry’ in
‘((struct mbox_list *)adapter)[96].tqh_last’ [-Wdangling-pointer=]
742 | TAILQ_INSERT_TAIL(head, entry, next);
| ^~~~~~~~~~~~~~~~~
../drivers/net/cxgbe/base/t4vf_hw.c: In function ‘t4vf_wr_mbox_core’:
../drivers/net/cxgbe/base/t4vf_hw.c:86:27: note: ‘entry’ declared here
86 | struct mbox_entry entry;
| ^~~~~
../drivers/net/cxgbe/base/t4vf_hw.c:86:27: note: ‘adapter’ declared here

Fixes: 3bd122eef2cc ("cxgbe/base: add hardware API for Chelsio T5 series adapters")
Cc: stable@dpdk.org

Reported-by: Ferruh Yigit <ferruh.yigit@intel.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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ethdev: hide internal structures

Move rte_eth_dev, rte_eth_dev_data, rte_eth_rxtx_callback and related
data into private header (ethdev_driver.h).
Few minor changes to keep DPDK building after that.

ethdev: hide internal structures

Move rte_eth_dev, rte_eth_dev_data, rte_eth_rxtx_callback and related
data into private header (ethdev_driver.h).
Few minor changes to keep DPDK building after that.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Tested-by: Feifei Wang <feifei.wang2@arm.com>

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net/cxgbe: disable Rx during port link down

When link goes down, disable the port's Rx path to drop the incoming
traffic closer to the wire, instead of accepting them in for further
Rx processing, o

net/cxgbe: disable Rx during port link down

When link goes down, disable the port's Rx path to drop the incoming
traffic closer to the wire, instead of accepting them in for further
Rx processing, only to eventually drop them at the port's RxQs. This
prevents unnecessary congestion in the Rx path. The port's Rx path
will be re-enabled once the link up event is received in the firmware
event queue.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: rework and simplify link handling

Rework and simplify link handling code. Remove redundant
variables in link configuration structure and directly
extract information from the 32-bit link

net/cxgbe: rework and simplify link handling

Rework and simplify link handling code. Remove redundant
variables in link configuration structure and directly
extract information from the 32-bit link capabilities.

Signed-off-by: Karra Satwik <kaara.satwik@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: improve Rx congestion control

Chelsio T6 NIC can support up to 8 priority channels to manage
congestion. So, increase to 8 congestion channels for T6. Also,
add Rxq state to avoid unneces

net/cxgbe: improve Rx congestion control

Chelsio T6 NIC can support up to 8 priority channels to manage
congestion. So, increase to 8 congestion channels for T6. Also,
add Rxq state to avoid unnecessarily ringing doorbell and polling
the hardware for more traffic when the Rxq is stopped.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: rework queue allocation between ports

Firmware returns the max queues that can be allocated on the entire
PF. The driver evenly distributes them across all the ports belonging
to the PF.

net/cxgbe: rework queue allocation between ports

Firmware returns the max queues that can be allocated on the entire
PF. The driver evenly distributes them across all the ports belonging
to the PF. However, some ports may need more queues than others and
this equal distribution scheme prevents accessing these other ports
unused queues. So, remove the equal distribution scheme and allow the
ports to allocate as many queues as they need.

Also remove the hardcoded 64 max limit on queue allocation. Instead,
use the max limit given by firmware.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: fix queue DMA ring leaks during port close

Free up the DMA memzones properly for all the port's queues during
port close. So, rework DMA ring allocation/free logic to use
rte_eth_dma_zone

net/cxgbe: fix queue DMA ring leaks during port close

Free up the DMA memzones properly for all the port's queues during
port close. So, rework DMA ring allocation/free logic to use
rte_eth_dma_zone_reserve()/rte_eth_dma_zone_free() helper functions
for allocating/freeing the memzones.

The firmware event queue doesn't have an associated freelist queue.
So, remove check that tries to give memzone name for a non-existent
freelist queue.

Also, add a missing free for the control queue mempools.

Fixes: 0462d115441d ("cxgbe: add device related operations")
Cc: stable@dpdk.org

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: add devargs to control filtermode and filtermask

Apart from the 4-tuple (IP src/dst addresses and TCP/UDP src/dst
port addresses), there are only 40-bits available to match other
fields i

net/cxgbe: add devargs to control filtermode and filtermask

Apart from the 4-tuple (IP src/dst addresses and TCP/UDP src/dst
port addresses), there are only 40-bits available to match other
fields in packet headers. Not all combinations of packet header
fields can fit in the 40-bit tuple.

Currently, the combination of packet header fields to match are
configured via filterMode for LETCAM filters and filterMask for
HASH filters in firmware config files (t5/t6-config.txt). So, add
devargs to allow User to dynamically select the filterMode and
filterMask combination during runtime, without having to modify the
firmware config files and reflashing them onto the adapter. A table
of supported combinations is maintained by the driver to internally
translate the User specified devargs combination to hardware's internal
format before writing the requested combination to hardware

Signed-off-by: Karra Satwik <kaara.satwik@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: support Source MAC Table

Source MAC Table (SMT) is used for storing Source MAC
addresses to be written in packets transmitted on the
wire. Hence, the SMT table can be used for overwriting

net/cxgbe: support Source MAC Table

Source MAC Table (SMT) is used for storing Source MAC
addresses to be written in packets transmitted on the
wire. Hence, the SMT table can be used for overwriting
Source MAC addresses in packets, hitting corresponding
filter rules inserted by the rte_flow API.

Query firmware for SMT start and size information available
to the underlying PF. Allocate and maintain the corresponding
driver's copy of the hardware SMT table, with appropriate
refcount mechanism. If SMT information is not available, then
use the entire hardware SMT table.

Signed-off-by: Karra Satwik <kaara.satwik@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: support flow API for matching all packets on VF

Add support to match all packets received on the underlying VF.

Use new firmware API to fetch the Virtual Interface Number (VIN)
allocated

net/cxgbe: support flow API for matching all packets on VF

Add support to match all packets received on the underlying VF.

Use new firmware API to fetch the Virtual Interface Number (VIN)
allocated to each VF by the firmware. The VIN is required to
write filter rules to match all packets on VFs, whose identifier
is beyond max 7-bit value (i.e. 127) in VIID.

If firmware doesn't support fetching the VIN information, then
fallback to manually retrieving the VIN value from the 7-bit field
in the VIID, which only supports in range of 0..127. In this case,
packets belonging to VFs, whose identifier is beyond 127 can't be
matched.

Signed-off-by: Karra Satwik <kaara.satwik@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: fix races on flow API operations

When rules are being inserted from multiple cores, there are several
race conditions during rte_flow operations.

For example, when inserting rules from 2

net/cxgbe: fix races on flow API operations

When rules are being inserted from multiple cores, there are several
race conditions during rte_flow operations.

For example, when inserting rules from 2 cores simultaneously, both
the cores try to fetch a free available filter entry and they both
end up fetching the same entry. Both of them start overwriting the
same filter entry before sending to firmware, which results in wrong
rule being inserted to hardware.

Fix the races by adding spinlock to serialize the rte_flow operations.

Fixes: ee61f5113b17 ("net/cxgbe: parse and validate flows")
Fixes: 9eb2c9a48072 ("net/cxgbe: implement flow create operation")
Fixes: da23bc9d33f4 ("net/cxgbe: implement flow destroy operation")
Fixes: 8d3c12e19368 ("net/cxgbe: implement flow query operation")
Fixes: 86910379d335 ("net/cxgbe: implement flow flush operation")
Cc: stable@dpdk.org

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: add devarg to control Tx coalescing

Remove compile time option to control Tx coalescing Latency vs
Throughput behavior. Add tx_mode_latency devarg instead, to
dynamically control Tx coale

net/cxgbe: add devarg to control Tx coalescing

Remove compile time option to control Tx coalescing Latency vs
Throughput behavior. Add tx_mode_latency devarg instead, to
dynamically control Tx coalescing behavior.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: separate VF only devargs

Rework devargs parsing logic to separate VF only args.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

net/cxgbe: use dynamic logging for debug prints

Remove compile time flags and use dynamic logging for debug prints.
Also remove rarely used debug logs in register access and datapath.

Signed-off-by

net/cxgbe: use dynamic logging for debug prints

Remove compile time flags and use dynamic logging for debug prints.
Also remove rarely used debug logs in register access and datapath.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: remove unnecessary cast

The device private pointer (dev_private) is of type void *
therefore no cast is necessary in C.

Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@net

net/cxgbe: remove unnecessary cast

The device private pointer (dev_private) is of type void *
therefore no cast is necessary in C.

Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

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net: add rte prefix to ether functions

Add 'rte_' prefix to functions:
- rename is_same_ether_addr() as rte_is_same_ether_addr().
- rename is_zero_ether_addr() as rte_is_zero_ether_addr().
- rename

net: add rte prefix to ether functions

Add 'rte_' prefix to functions:
- rename is_same_ether_addr() as rte_is_same_ether_addr().
- rename is_zero_ether_addr() as rte_is_zero_ether_addr().
- rename is_unicast_ether_addr() as rte_is_unicast_ether_addr().
- rename is_multicast_ether_addr() as rte_is_multicast_ether_addr().
- rename is_broadcast_ether_addr() as rte_is_broadcast_ether_addr().
- rename is_universal_ether_addr() as rte_is_universal_ether_addr().
- rename is_local_admin_ether_addr() as rte_is_local_admin_ether_addr().
- rename is_valid_assigned_ether_addr() as rte_is_valid_assigned_ether_addr().
- rename eth_random_addr() as rte_eth_random_addr().
- rename ether_addr_copy() as rte_ether_addr_copy().
- rename ether_format_addr() as rte_ether_format_addr().

Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Reviewed-by: Stephen Hemminger <stephen@networkplumber.org>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

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net: add rte prefix to ether structures

Add 'rte_' prefix to structures:
- rename struct ether_addr as struct rte_ether_addr.
- rename struct ether_hdr as struct rte_ether_hdr.
- rename struct vlan_

net: add rte prefix to ether structures

Add 'rte_' prefix to structures:
- rename struct ether_addr as struct rte_ether_addr.
- rename struct ether_hdr as struct rte_ether_hdr.
- rename struct vlan_hdr as struct rte_vlan_hdr.
- rename struct vxlan_hdr as struct rte_vxlan_hdr.
- rename struct vxlan_gpe_hdr as struct rte_vxlan_gpe_hdr.

Do not update the command line library to avoid adding a dependency to
librte_net.

Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Reviewed-by: Stephen Hemminger <stephen@networkplumber.org>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

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net/cxgbe: remove unused code in Rx path

All Rx packet handling is done in process_responses() and hence
t4_ethrx_handler() never gets called. So, remove it.

Signed-off-by: Vishal Kulkarni <vishal@

net/cxgbe: remove unused code in Rx path

All Rx packet handling is done in process_responses() and hence
t4_ethrx_handler() never gets called. So, remove it.

Signed-off-by: Vishal Kulkarni <vishal@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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net/cxgbe: use relative paths for includes

The Intel C++ compiler is not able to locate the header files without
relative paths in Windows build. Following errors are seen for these
header files.

C

net/cxgbe: use relative paths for includes

The Intel C++ compiler is not able to locate the header files without
relative paths in Windows build. Following errors are seen for these
header files.

C:\> base\common.h(9): error : cannot open source file "cxgbe_compat.h"
#include "cxgbe_compat.h"
^
[...]

Fix by explicitly stating header file location using relative paths.
Also, remove automatically including header files for Linux, to keep
it consistent across both OS.

Build Environment:
1. Target OS: Microsoft Windows Server 2016
2. Compiler: Intel C++ Compiler from Intel Parallel Studio XE 2019 [1]
3. Development Tools:
3.1 Microsoft Visual Studio 2017 Professional
3.2 Windows Software Development Kit (SDK) v10.0.17763
3.3 Windows Driver Kit (WDK) v10.0.17763

[1] https://software.intel.com/en-us/parallel-studio-xe

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

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