| /netbsd-src/sys/external/isc/atheros_hal/ic/ |
| H A D | ah_osdep.h | 93 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) argument
94 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) argument
112 #define OS_REG_WRITE(_ah, _reg, _val) do { \ argument
120 #define OS_REG_READ(_ah, _reg) \ argument
125 #define OS_REG_WRITE(_ah, _reg, _val) \ argument
127 #define OS_REG_READ(_ah, _reg) \ argument
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| /netbsd-src/sys/arch/arm/at91/ |
| H A D | at91rm9200reg.h | 198 #define PIOA_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOA_BASE + (_reg))) argument
199 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOA_BASE + (_reg))) = (_val)… argument
200 #define PIOB_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOB_BASE + (_reg))) argument
201 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOB_BASE + (_reg))) = (_val)… argument
202 #define PIOC_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOC_BASE + (_reg))) argument
203 #define PIOC_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOC_BASE + (_reg))) = (_val)… argument
204 #define PIOD_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOD_BASE + (_reg))) argument
205 #define PIOD_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOD_BASE + (_reg))) = (_val)… argument
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| H A D | at91sam9261reg.h | 211 #define PIOA_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg))) argument
212 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg))) = (_val… argument
213 #define PIOB_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg))) argument
214 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg))) = (_val… argument
215 #define PIOC_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOC_BASE + (_reg))) argument
216 #define PIOC_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOC_BASE + (_reg))) = (_val… argument
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| H A D | at91sam9260reg.h | 213 #define PIOA_READ(_reg) *((volatile uint32_t *)(AT91SAM9260_PIOA_BASE + (_reg))) argument
214 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9260_PIOA_BASE + (_reg))) = (_val… argument
215 #define PIOB_READ(_reg) *((volatile uint32_t *)(AT91SAM9260_PIOB_BASE + (_reg))) argument
216 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9260_PIOB_BASE + (_reg))) = (_val… argument
217 #define PIOC_READ(_reg) *((volatile uint32_t *)(AT91SAM9260_PIOC_BASE + (_reg))) argument
218 #define PIOC_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9260_PIOC_BASE + (_reg))) = (_val… argument
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| H A D | at91pio.c | 69 #define PIO_READ(_sc, _reg) bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_reg)) argument
70 #define PIO_WRITE(_sc, _reg, _val) bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_reg), (_val)) argument
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| /netbsd-src/sys/arch/arm/nxp/ |
| H A D | imx_ccm.h | 87 #define IMX_GATE(_id, _name, _pname, _reg, _mask) \ argument
89 #define IMX_GATE_INDEX(_id, _regidx, _name, _pname, _reg, _mask) \ argument
102 #define IMX_ROOT_GATE(_id, _name, _pname, _reg) \ argument
104 #define IMX_ROOT_GATE_INDEX(_id, _regidx, _name, _pname, _reg) \ argument
124 #define IMX_COMPOSITE(_id, _name, _parents, _reg, _flags) \ argument
127 #define IMX_COMPOSITE_INDEX(_id, _regidx, _name, _parents, _reg, _flags) \ argument
161 #define IMX_PLL(_id, _name, _parent, _reg, _div_mask, _flags) \ argument
163 #define IMX_PLL_INDEX(_id, _regidx, _name, _parent, _reg, _div_mask, _flags) \ argument
235 #define IMX_MUX(_id, _name, _parents, _reg, _sel) \ argument
238 #define IMX_MUX_INDEX(_id, _regidx, _name, _parents, _reg, _sel) \ argument
[all …]
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| H A D | imx6_ccmvar.h | 183 #define CLK_PFD(_name, _parent, _reg, _index) { \ argument
195 #define CLK_PLL(_name, _parent, _type, _reg, _mask, _powerdown, _ref) { \ argument
210 #define CLK_DIV(_name, _parent, _reg, _mask) { \ argument
224 #define CLK_DIV_BUSY(_name, _parent, _reg, _mask, _busy_reg, _busy_mask) { \ argument
240 #define CLK_DIV_TABLE(_name, _parent, _reg, _mask, _tbl) { \ argument
255 #define CLK_MUX(_name, _parents, _base, _reg, _mask) { \ argument
270 #define CLK_MUX_BUSY(_name, _parents, _reg, _mask, _busy_reg, _busy_mask) { \ argument
287 #define CLK_GATE(_name, _parent, _base, _reg, _mask) { \ argument
301 #define CLK_GATE_EXCLUSIVE(_name, _parent, _base, _reg, _mask, _exclusive_mask) { \ argument
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| H A D | imx7d_ccm.c | 101 #define ANATOP_MUX(_id, _name, _parents, _reg, _mask) \ argument
103 #define ANATOP_GATE(_id, _name, _parent, _reg, _mask) \ argument
105 #define ANATOP_PLL(_id, _name, _parent, _reg, _div_mask, _flags) \ argument
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| /netbsd-src/sys/dev/fdt/ |
| H A D | syscon.h | 47 #define syscon_read_4(_syscon, _reg) \ argument
50 #define syscon_write_4(_syscon, _reg, _val) \ argument
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| H A D | fdt_regulator.c | 40 #define REGULATOR_TO_RC(_reg) \ argument
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| /netbsd-src/sys/arch/arm/sunxi/ |
| H A D | sunxi_ccu.h | 47 #define SUNXI_CCU_RESET(_id, _reg, _bit) \ argument
81 #define SUNXI_CCU_GATE(_id, _name, _pname, _reg, _bit) \ argument
129 #define SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \ argument
150 #define SUNXI_CCU_NKMP(_id, _name, _parent, _reg, _n, _k, _m, \ argument
182 #define SUNXI_CCU_NM(_id, _name, _parents, _reg, _n, _m, _sel, \ argument
228 SUNXI_CCU_DIV(_id,_name,_parents,_reg,_div,_sel,_flags) global() argument
233 SUNXI_CCU_DIV_GATE(_id,_name,_parents,_reg,_div,_sel,_enable,_flags) global() argument
288 SUNXI_CCU_PREDIV(_id,_name,_parents,_reg,_prediv,_prediv_sel,_div,_sel,_flags) global() argument
293 SUNXI_CCU_PREDIV_FIXED(_id,_name,_parents,_reg,_prediv,_prediv_sel,_prediv_fixed,_div,_sel,_flags) global() argument
326 SUNXI_CCU_PHASE(_id,_name,_parent,_reg,_mask) global() argument
391 SUNXI_CCU_FRACTIONAL(_id,_name,_parent,_reg,_m,_m_min,_m_max,_div_en,_frac_sel,_frac0,_frac1,_prediv,_prediv_val,_enable,_flags) global() argument
431 SUNXI_CCU_MUX(_id,_name,_parents,_reg,_sel,_flags) global() argument
[all...] |
| /netbsd-src/sys/arch/arm/ti/ |
| H A D | am3_prcm.c | 129 #define AM3_PRCM_HWMOD_PER(_name, _reg, _parent) \ argument
131 #define AM3_PRCM_HWMOD_PER_DISP(_name, _reg, _parent) \ argument
133 #define AM3_PRCM_HWMOD_WKUP(_name, _reg, _parent) \ argument
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| H A D | ti_prcm.h | 143 #define TI_PRCM_HWMOD(_name, _reg, _parent, _enable) \ argument
146 #define TI_PRCM_HWMOD_MASK(_name, _reg, _mask, _parent, _enable, _flags) \ argument
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| /netbsd-src/sys/arch/arm/amlogic/ |
| H A D | meson_clk.h | 48 #define MESON_CLK_RESET(_id, _reg, _bit) \ argument
105 #define MESON_CLK_GATE_FLAGS(_id, _name, _pname, _reg, _bit, _flags) \ argument
118 #define MESON_CLK_GATE(_id, _name, _pname, _reg, _bit) \ argument
142 #define MESON_CLK_DIV(_id, _name, _parent, _reg, _div, _flags) \ argument
199 #define MESON_CLK_MUX_RATE(_id, _name, _parents, _reg, _sel, \ argument
215 #define MESON_CLK_MUX(_id, _name, _parents, _reg, _sel, _flags) \ argument
237 #define MESON_CLK_PLL_REG(_reg, _mask) \ argument
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| H A D | mesong12a_pinctrl.c | 337 #define GPIO_MUX_PINCTRL_GROUP(_name, _reg, _off, _group, _func) \ argument
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| /netbsd-src/sys/arch/alpha/tlsb/ |
| H A D | tlsbreg.h | 68 #define TLSB_NODE_REG_ADDR(_node, _reg) \ argument
72 #define TLSB_GET_NODEREG(_node, _reg) \ argument
74 #define TLSB_PUT_NODEREG(_node, _reg, _val) \ argument
83 #define TLSB_BCAST_REG_ADDR(_reg) KV((long)(TLSB_BCASE_BASE + (_reg))) argument
86 #define TLSB_GET_BCASTREG(_reg) \ argument
88 #define TLSB_PUT_BCASTREG(_reg, _val) \ argument
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| /netbsd-src/sys/arch/arm/samsung/ |
| H A D | exynos5410_clock.c | 147 #define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \ argument
161 #define CLK_MUXA(_name, _alias, _reg, _bits, _p) \ argument
164 #define CLK_MUX(_name, _reg, _bits, _p) \ argument
167 #define CLK_DIVF(_name, _parent, _reg, _bits, _f) { \ argument
179 #define CLK_DIV(_name, _parent, _reg, _bits) \ argument
182 #define CLK_GATE(_name, _parent, _reg, _bits, _f) { \ argument
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| H A D | exynos5422_clock.c | 291 #define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \ argument
305 #define CLK_MUXA(_name, _alias, _reg, _bits, _p) \ argument
308 #define CLK_MUX(_name, _reg, _bits, _p) \ argument
311 #define CLK_DIV(_name, _parent, _reg, _bits) { \ argument
322 #define CLK_GATE(_name, _parent, _reg, _bits, _f) { \ argument
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| /netbsd-src/sys/external/isc/atheros_hal/dist/ar5312/ |
| H A D | ar5312reg.h | 31 #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val); argument
32 #define REG_READ(_reg) *((volatile uint32_t *)(_reg)) argument
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| H A D | reg.h | 82 #define REG_50080_TO_PIPE(_reg) ({ \ argument
89 #define REG_50080_TO_PLANE(_reg) ({ \ argument
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| /netbsd-src/sys/arch/arm/rockchip/ |
| H A D | rk_cru.h | 190 #define RK_ARM(_id, _name, _parents, _reg, _mux_mask, _mux_main, _mux_alt, _div_mask, _rates) \ argument
355 #define RK_GATE(_id, _name, _pname, _reg, _bit) \ argument
391 #define RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, _flags) \ argument
405 #define RK_MUX(_id, _name, _parents, _reg, _mask) \ argument
407 #define RK_MUXGRF(_id, _name, _parents, _reg, _mask) \ argument
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/ |
| H A D | i915_cmd_parser.c | 579 #define REG32(_reg, ...) \ argument
589 #define REG64(_reg) \ argument
593 #define REG64_IDX(_reg, idx) \ argument
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| /netbsd-src/sys/arch/arm/nvidia/ |
| H A D | tegra124_car.c | 310 #define CLK_MUX(_name, _reg, _bits, _p) { \ argument
332 #define CLK_DIV(_name, _parent, _reg, _bits) { \ argument
386 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ argument
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| H A D | tegra210_car.c | 322 #define CLK_MUX(_name, _reg, _bits, _p) { \ argument
344 #define CLK_DIV(_name, _parent, _reg, _bits) { \ argument
404 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ argument
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| /netbsd-src/external/bsd/pcc/dist/pcc/mip/ |
| H A D | node.h | 68 int _reg; member
|