Lines Matching defs:_reg
47 #define SUNXI_CCU_RESET(_id, _reg, _bit) \
49 .reg = (_reg), \
81 #define SUNXI_CCU_GATE(_id, _name, _pname, _reg, _bit) \
87 .u.gate.reg = (_reg), \
129 #define SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \
134 .u.nkmp.reg = (_reg), \
150 #define SUNXI_CCU_NKMP(_id, _name, _parent, _reg, _n, _k, _m, \
152 SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \
182 #define SUNXI_CCU_NM(_id, _name, _parents, _reg, _n, _m, _sel, \
187 .u.nm.reg = (_reg), \
228 #define SUNXI_CCU_DIV(_id, _name, _parents, _reg, _div, \
230 SUNXI_CCU_DIV_GATE(_id, _name, _parents, _reg, _div, \
233 #define SUNXI_CCU_DIV_GATE(_id, _name, _parents, _reg, _div, \
238 .u.div.reg = (_reg), \
288 #define SUNXI_CCU_PREDIV(_id, _name, _parents, _reg, _prediv, \
290 SUNXI_CCU_PREDIV_FIXED(_id, _name, _parents, _reg, _prediv, \
293 #define SUNXI_CCU_PREDIV_FIXED(_id, _name, _parents, _reg, _prediv, \
298 .u.prediv.reg = (_reg), \
326 #define SUNXI_CCU_PHASE(_id, _name, _parent, _reg, _mask) \
330 .u.phase.reg = (_reg), \
391 #define SUNXI_CCU_FRACTIONAL(_id, _name, _parent, _reg, _m, _m_min, _m_max, \
397 .u.fractional.reg = (_reg), \
431 #define SUNXI_CCU_MUX(_id, _name, _parents, _reg, _sel, _flags) \
436 .u.mux.reg = (_reg), \