| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupSetCC.cpp | 123 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
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| H A D | X86FrameLowering.cpp | 958 ZeroReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass), emitStackProbeInlineWindowsCoreCLR64() local
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| /llvm-project/llvm/tools/llvm-exegesis/lib/Mips/ |
| H A D | Target.cpp | 78 unsigned ZeroReg; in loadImmediate() local
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| /llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/ |
| H A D | TargetTest.cpp | 46 const unsigned ZeroReg = IsGPR32 ? Mips::ZERO : Mips::ZERO_64; in IsLoadLow16BitImm() local
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| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 87 unsigned Opc = 0, ZeroReg = 0; copyPhysReg() local
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| H A D | MipsAsmPrinter.cpp | 141 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; emitPseudoIndirectBranch() local
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| H A D | MipsSEISelDAGToDAG.cpp | 85 unsigned DstReg = 0, ZeroReg = 0; replaceUsesWithZeroReg() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4423 copyGPRRegTuple(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,DebugLoc DL,unsigned DestReg,unsigned SrcReg,bool KillSrc,unsigned Opcode,unsigned ZeroReg,llvm::ArrayRef<unsigned> Indices) const copyGPRRegTuple() argument
5921 canCombine(MachineBasicBlock & MBB,MachineOperand & MO,unsigned CombineOpc,unsigned ZeroReg=0,bool CheckZeroReg=false) canCombine() argument
5954 canCombineWithMUL(MachineBasicBlock & MBB,MachineOperand & MO,unsigned MulOpc,unsigned ZeroReg) canCombineWithMUL() argument
6097 __anon20eab7760f02(int Opcode, int Operand, unsigned ZeroReg, unsigned Pattern) getMaddPatterns() argument
7046 unsigned BitSize, OrrOpc, ZeroReg; genAlternativeCodeSequence() local
7108 unsigned SubOpc, ZeroReg; genAlternativeCodeSequence() local
7156 unsigned BitSize, OrrOpc, ZeroReg; genAlternativeCodeSequence() local
[all...] |
| H A D | AArch64ExpandPseudoInsts.cpp | 237 expandCMP_SWAP(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,unsigned LdarOp,unsigned StlrOp,unsigned CmpOp,unsigned ExtendImm,unsigned ZeroReg,MachineBasicBlock::iterator & NextMBBI) expandCMP_SWAP() argument
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| H A D | AArch64FastISel.cpp | 384 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; materializeInt() local
4935 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; selectSDiv() local
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| H A D | AArch64ISelDAGToDAG.cpp | 3692 unsigned ZeroReg; tryShiftAmountMod() local
3712 unsigned ZeroReg; tryShiftAmountMod() local
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| H A D | AArch64ISelLowering.cpp | 21649 unsigned ZeroReg; replaceZeroVectorStore() local
[all...] |
| /llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 950 SDValue ZeroReg = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8); LowerINLINEASM() local
1931 Register ZeroReg = MRI.createVirtualRegister(&AVR::GPR8RegClass); insertMultibyteShift() local
[all...] |
| H A D | AVRExpandPseudoInsts.cpp | 459 Register ZeroReg = MI.getOperand(2).getReg(); in expand() local
1494 Register ZeroReg = MI.getOperand(3).getReg(); in expandROLBRd() local
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| /llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GIMatchTableExecutorImpl.h | 1088 uint16_t ZeroReg = readU16(); executeMatchTable() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 552 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
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| H A D | ARMFastISel.cpp | 1476 unsigned ZeroReg = fastMaterializeConstant(Zero); SelectCmp() local
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| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1600 Register ZeroReg = legalizeIntrinsic() local
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| /llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInstructionSelector.cpp | 1663 Register ZeroReg = buildZerosVal(ResType, I); selectSelect() local
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| /llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2782 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); loadImmediate() local
4259 unsigned ZeroReg; expandDivRem() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2098 MCRegister ZeroReg; onlyFoldImmediate() local
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| H A D | PPCISelDAGToDAG.cpp | 6310 SDValue ZeroReg = Select() local
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| H A D | PPCISelLowering.cpp | 12246 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; EmitPartwordAtomicBinary() local
13299 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; EmitInstrWithCustomInserter() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 8809 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); convertNonUniformLoopRegion() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2292 Register ZeroReg; applyCombineUnmergeZExtToZExt() local
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