/llvm-project/clang/lib/AST/ |
H A D | ASTStructuralEquivalence.cpp | 956 const auto *Vec1 = cast<DependentSizedExtVectorType>(T1); IsStructurallyEquivalent() local 968 const auto *Vec1 = cast<DependentVectorType>(T1); IsStructurallyEquivalent() local 983 const auto *Vec1 = cast<VectorType>(T1); IsStructurallyEquivalent() local [all...] |
H A D | ExprConstant.cpp | 11072 const Expr *Vec1 = E->getExpr(0); VisitShuffleVectorExpr() local
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/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | EarlyCSE.cpp | 1012 auto *Vec1 = dyn_cast<ConstantVector>(Mask1); isNonTargetIntrinsicMatch() local
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/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 1913 SDValue Vec1 = IntermedVals[0].first; ExpandBVWithShuffles() local 2028 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); ExpandBUILD_VECTOR() local
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H A D | SelectionDAG.cpp | 12348 SDValue Vec1 = getBuildVector(VT1, dl, Scalars1); UnrollVectorOp() local
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/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAGHVX.cpp | 2637 SDValue Vec1 = N->getOperand(1); selectShuffle() local
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H A D | HexagonISelLoweringHVX.cpp | 1880 SDValue Vec1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, LowerHvxCttz() local
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/llvm-project/llvm/lib/Bitcode/Reader/ |
H A D | BitcodeReader.cpp | 5394 Value *Vec1, *Vec2, *Mask; parseFunctionBody() local
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/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 7426 SDValue Vec1 = SVN->getOperand(VecIdx1); lowerVECTOR_SHUFFLE() local 14457 SDValue Vec1 = Op1.getOperand(0); performFMACombine() local [all...] |
/llvm-project/llvm/lib/Transforms/Vectorize/ |
H A D | SLPVectorizer.cpp | 543 Value *Vec1 = nullptr; isFixedVectorShuffle() local 12522 Value *Vec1 = nullptr; processBuildVector() local [all...] |
/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 14368 SDValue Vec1 = Op.getOperand(1); LowerINSERT_SUBVECTOR() local [all...] |
/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 49143 SDValue Vec1 = N1.getOperand(0); combineBitOpWithMOVMSK() local [all...] |