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Searched defs:VT (Results 1 – 25 of 230) sorted by relevance

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/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineValueType.h
H A DTargetLowering.h460 shouldExpandGetActiveLaneMask(EVT VT,EVT OpVT) shouldExpandGetActiveLaneMask() argument
471 shouldExpandCttzElements(EVT VT) shouldExpandCttzElements() argument
475 shouldReassociateReduction(unsigned RedOpc,EVT VT) shouldReassociateReduction() argument
497 getPreferredVectorAction(MVT VT) getPreferredVectorAction() argument
533 isIntDivCheap(EVT VT,AttributeList Attr) isIntDivCheap() argument
536 hasStandaloneRem(EVT VT) hasStandaloneRem() argument
660 isCtpopFast(EVT VT) isCtpopFast() argument
666 getCustomCtpopCost(EVT VT,ISD::CondCode Cond) getCustomCtpopCost() argument
710 convertSetCCLogicToBitwiseLogic(EVT VT) convertSetCCLogicToBitwiseLogic() argument
719 MVT VT = MVT::getIntegerVT(NumBits); hasFastEqualityCompare() local
848 preferedOpcodeForCmpEqPiecesOfOperand(EVT VT,unsigned ShiftOpc,bool MayTransformRotate,const APInt & ShiftOrRotateAmt,const std::optional<APInt> & AndMask) preferedOpcodeForCmpEqPiecesOfOperand() argument
859 preferIncOfAddToSubOfNot(EVT VT) preferIncOfAddToSubOfNot() argument
866 preferABDSToABSWithNSW(EVT VT) preferABDSToABSWithNSW() argument
877 preferSextInRegOfTruncate(EVT TruncVT,EVT VT,EVT ExtVT) preferSextInRegOfTruncate() argument
912 enableAggressiveFMAFusion(EVT VT) enableAggressiveFMAFusion() argument
1002 getRepRegClassFor(MVT VT) getRepRegClassFor() argument
1009 getRepRegClassCostFor(MVT VT) getRepRegClassCostFor() argument
1031 isTypeLegal(EVT VT) isTypeLegal() argument
1048 getTypeAction(MVT VT) getTypeAction() argument
1052 setTypeAction(MVT VT,LegalizeTypeAction Action) setTypeAction() argument
1081 getTypeAction(LLVMContext & Context,EVT VT) getTypeAction() argument
1084 getTypeAction(MVT VT) getTypeAction() argument
1094 getTypeToTransformTo(LLVMContext & Context,EVT VT) getTypeToTransformTo() argument
1102 getTypeToExpandTo(LLVMContext & Context,EVT VT) getTypeToExpandTo() argument
1134 getVectorTypeBreakdownForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) getVectorTypeBreakdownForCallingConv() argument
1208 getOperationAction(unsigned Op,EVT VT) getOperationAction() argument
1220 isSupportedFixedPointOperation(unsigned Op,EVT VT,unsigned Scale) isSupportedFixedPointOperation() argument
1229 getFixedPointOperationAction(unsigned Op,EVT VT,unsigned Scale) getFixedPointOperationAction() argument
1258 getStrictFPOperationAction(unsigned Op,EVT VT) getStrictFPOperationAction() argument
1317 isOperationCustom(unsigned Op,EVT VT) isOperationCustom() argument
1379 isOperationExpand(unsigned Op,EVT VT) isOperationExpand() argument
1384 isOperationLegal(unsigned Op,EVT VT) isOperationLegal() argument
1452 getIndexedLoadAction(unsigned IdxMode,MVT VT) getIndexedLoadAction() argument
1457 isIndexedLoadLegal(unsigned IdxMode,EVT VT) isIndexedLoadLegal() argument
1466 getIndexedStoreAction(unsigned IdxMode,MVT VT) getIndexedStoreAction() argument
1471 isIndexedStoreLegal(unsigned IdxMode,EVT VT) isIndexedStoreLegal() argument
1480 getIndexedMaskedLoadAction(unsigned IdxMode,MVT VT) getIndexedMaskedLoadAction() argument
1485 isIndexedMaskedLoadLegal(unsigned IdxMode,EVT VT) isIndexedMaskedLoadLegal() argument
1494 getIndexedMaskedStoreAction(unsigned IdxMode,MVT VT) getIndexedMaskedStoreAction() argument
1499 isIndexedMaskedStoreLegal(unsigned IdxMode,EVT VT) isIndexedMaskedStoreLegal() argument
1507 shouldExtendGSIndex(EVT VT,EVT & EltTy) shouldExtendGSIndex() argument
1531 getCondCodeAction(ISD::CondCode CC,MVT VT) getCondCodeAction() argument
1544 isCondCodeLegal(ISD::CondCode CC,MVT VT) isCondCodeLegal() argument
1550 isCondCodeLegalOrCustom(ISD::CondCode CC,MVT VT) isCondCodeLegalOrCustom() argument
1557 getTypeToPromoteTo(unsigned Op,MVT VT) getTypeToPromoteTo() argument
1641 getRegisterType(MVT VT) getRegisterType() argument
1647 getRegisterType(LLVMContext & Context,EVT VT) getRegisterType() argument
1701 getRegisterTypeForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT) getRegisterTypeForCallingConv() argument
1710 getNumRegistersForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT) getNumRegistersForCallingConv() argument
1745 hasBigEndianPartOrdering(EVT VT,const DataLayout & DL) hasBigEndianPartOrdering() argument
2302 shouldNormalizeToSelectSequence(LLVMContext & Context,EVT VT) shouldNormalizeToSelectSequence() argument
2314 isProfitableToCombineMinNumMaxNum(EVT VT) isProfitableToCombineMinNumMaxNum() argument
2319 convertSelectOfConstantsToMath(EVT VT) convertSelectOfConstantsToMath() argument
2329 decomposeMulByConstant(LLVMContext & Context,EVT VT,SDValue C) decomposeMulByConstant() argument
2442 addRegisterClass(MVT VT,const TargetRegisterClass * RC) addRegisterClass() argument
2459 setOperationAction(unsigned Op,MVT VT,LegalizeAction Action) setOperationAction() argument
2463 setOperationAction(ArrayRef<unsigned> Ops,MVT VT,LegalizeAction Action) setOperationAction() argument
2470 for (auto VT : VTs) setOperationAction() local
2508 setIndexedLoadAction(ArrayRef<unsigned> IdxModes,MVT VT,LegalizeAction Action) setIndexedLoadAction() argument
2516 for (auto VT : VTs) setIndexedLoadAction() local
2525 setIndexedStoreAction(ArrayRef<unsigned> IdxModes,MVT VT,LegalizeAction Action) setIndexedStoreAction() argument
2533 for (auto VT : VTs) setIndexedStoreAction() local
2542 setIndexedMaskedLoadAction(unsigned IdxMode,MVT VT,LegalizeAction Action) setIndexedMaskedLoadAction() argument
2552 setIndexedMaskedStoreAction(unsigned IdxMode,MVT VT,LegalizeAction Action) setIndexedMaskedStoreAction() argument
2559 setCondCodeAction(ArrayRef<ISD::CondCode> CCs,MVT VT,LegalizeAction Action) setCondCodeAction() argument
2575 for (auto VT : VTs) setCondCodeAction() local
2902 EVT VT = getValueType(DL, Ext->getType()); isExtLoad() local
3092 isFNegFree(EVT VT) isFNegFree() argument
3099 isFAbsFree(EVT VT) isFAbsFree() argument
3170 generateFMAsInMachineCombiner(EVT VT,CodeGenOptLevel OptLevel) generateFMAsInMachineCombiner() argument
3186 shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,EVT VT) shouldFoldSelectWithIdentityConstant() argument
3219 isExtractVecEltCheap(EVT VT,unsigned Index) isExtractVecEltCheap() argument
3227 shouldFormOverflowOp(unsigned Opcode,EVT VT,bool MathUsed) shouldFormOverflowOp() argument
3257 shouldAvoidTransformToShift(EVT VT,unsigned Amount) shouldAvoidTransformToShift() argument
3263 shouldFoldSelectWithSingleBitTest(EVT VT,const APInt & AndMask) shouldFoldSelectWithSingleBitTest() argument
3275 shouldConvertFpToSat(unsigned Op,EVT FPVT,EVT VT) shouldConvertFpToSat() argument
3533 setIndexedModeAction(unsigned IdxMode,MVT VT,unsigned Shift,LegalizeAction Action) setIndexedModeAction() argument
3542 getIndexedModeAction(unsigned IdxMode,MVT VT,unsigned Shift) getIndexedModeAction() argument
4215 isTypeDesirableForOp(unsigned,EVT VT) isTypeDesirableForOp() argument
4661 getTypeForExtReturn(LLVMContext & Context,EVT VT,ISD::NodeType) getTypeForExtReturn() argument
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp128 for (auto VT : MFI.getParams()) in WebAssemblyFunctionInfo() local
159 for (auto VT : YamlMFI.Params) in initializeBaseYamlFields() local
48 for (EVT VT : VTs) { computeLegalValueVTs() local
126 for (auto VT : MFI.getParams()) WebAssemblyFunctionInfo() local
157 for (auto VT : YamlMFI.Params) initializeBaseYamlFields() local
[all...]
H A DWebAssemblyMachineFunctionInfo.h81 void addParam(MVT VT) { Params.push_back(VT); } in addParam() argument
84 void addResult(MVT VT) { Results.push_back(VT); } in addResult() argument
93 void setLocal(size_t i, MVT VT) { Locals[i] = VT; } in setLocal() argument
94 void addLocal(MVT VT) { Locals.push_back(VT); } in addLocal() argument
/freebsd-src/contrib/llvm-project/llvm/utils/TableGen/
H A DVTEmitter.cpp113 for (const auto *VT in run() local
37 for (auto *VT : ValueTypes) { run() local
66 for (const auto *VT : VTsByNumber) { run() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp229 static MVT scaleVectorType(MVT VT) { in scaleVectorType() argument
257 static void genShuffleBland(MVT VT, ArrayRef<int> Mask, in genShuffleBland() argument
287 static void reorderSubVector(MVT VT, SmallVectorImpl<Value *> &TransposedMatrix, in reorderSubVector() argument
327 MVT VT = MVT::v8i16; in interleave8bitStride4VF8() local
367 MVT VT = MVT::getVectorVT(MVT::i8, NumOfElm); interleave8bitStride4() local
436 createShuffleStride(MVT VT,int Stride,SmallVectorImpl<int> & Mask) createShuffleStride() argument
450 setGroupSize(MVT VT,SmallVectorImpl<int> & SizeInfo) setGroupSize() argument
473 DecodePALIGNRMask(MVT VT,unsigned Imm,SmallVectorImpl<int> & ShuffleMask,bool AlignDirection=true,bool Unary=false) DecodePALIGNRMask() argument
558 MVT VT = MVT::getVT(Shuffles[0]->getType()); deinterleave8bitStride3() local
606 group2Shuffle(MVT VT,SmallVectorImpl<int> & Mask,SmallVectorImpl<int> & Output) group2Shuffle() argument
641 MVT VT = MVT::getVectorVT(MVT::i8, VecElems); interleave8bitStride3() local
[all...]
H A DX86FastISel.cpp290 isTypeLegal(Type * Ty,MVT & VT,bool AllowI1) isTypeLegal() argument
316 X86FastEmitLoad(MVT VT,X86AddressMode & AM,MachineMemOperand * MMO,unsigned & ResultReg,unsigned Alignment) X86FastEmitLoad() argument
479 X86FastEmitStore(EVT VT,unsigned ValReg,X86AddressMode & AM,MachineMemOperand * MMO,bool Aligned) X86FastEmitStore() argument
652 X86FastEmitStore(EVT VT,const Value * Val,X86AddressMode & AM,MachineMemOperand * MMO,bool Aligned) X86FastEmitStore() argument
1149 MVT VT; X86SelectStore() local
1338 MVT VT; X86SelectLoad() local
1357 X86ChooseCmpOpcode(EVT VT,const X86Subtarget * Subtarget) X86ChooseCmpOpcode() argument
1384 X86ChooseCmpImmediateOpcode(EVT VT,const ConstantInt * RHSC) X86ChooseCmpImmediateOpcode() argument
1402 X86FastEmitCompare(const Value * Op0,const Value * Op1,EVT VT,const DebugLoc & CurMIMD) X86FastEmitCompare() argument
1438 MVT VT; X86SelectCmp() local
1647 EVT VT = TLI.getValueType(DL, CI->getOperand(0)->getType()); X86SelectBranch() local
1831 MVT VT; X86SelectShift() local
1918 MVT VT; X86SelectDivRem() local
2558 MVT VT; TryEmitSmallMemcpy() local
2662 MVT VT; fastLowerIntrinsicCall() local
2793 MVT VT; fastLowerIntrinsicCall() local
2857 MVT VT; fastLowerIntrinsicCall() local
2982 MVT VT; fastLowerIntrinsicCall() local
3039 MVT VT; fastLowerIntrinsicCall() local
3162 MVT VT = TLI.getSimpleValueType(DL, Arg.getType()); fastLowerArguments() local
3302 MVT VT; fastLowerCall() local
3724 X86MaterializeInt(const ConstantInt * CI,MVT VT) X86MaterializeInt() argument
3772 X86MaterializeFP(const ConstantFP * CFP,MVT VT) X86MaterializeFP() argument
3846 X86MaterializeGV(const GlobalValue * GV,MVT VT) X86MaterializeGV() argument
3890 MVT VT = CEVT.getSimpleVT(); fastMaterializeConstant() local
3954 MVT VT; fastMaterializeFloatZero() local
[all...]
H A DX86ISelLowering.cpp163 for (MVT VT : MVT::integer_valuetypes()) X86TargetLowering() local
552 __anon973982070202(MVT VT, LegalizeAction Action) X86TargetLowering() argument
911 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { X86TargetLowering() local
2100 __anon973982070302(MVT VT) X86TargetLowering() argument
2847 useVPTERNLOG(const X86Subtarget & Subtarget,MVT VT) useVPTERNLOG() argument
2952 MVT VT = MVT::getVT(I.getArgOperand(1)->getType()); getTgtMemIntrinsic() local
3001 isFPImmLegal(const APFloat & Imm,EVT VT,bool ForCodeSize) const isFPImmLegal() argument
3024 EVT VT = Load->getValueType(0); shouldReduceLoadWidth() local
3073 decomposeMulByConstant(LLVMContext & Context,EVT VT,SDValue C) const decomposeMulByConstant() argument
3138 shouldFormOverflowOp(unsigned Opcode,EVT VT,bool) const shouldFormOverflowOp() argument
3215 EVT VT = Y.getValueType(); hasAndNotCompare() local
3231 EVT VT = Y.getValueType(); hasAndNot() local
3275 preferedOpcodeForCmpEqPiecesOfOperand(EVT VT,unsigned ShiftOpc,bool MayTransformRotate,const APInt & ShiftOrRotateAmt,const std::optional<APInt> & AndMask) const preferedOpcodeForCmpEqPiecesOfOperand() argument
3353 EVT VT = N->getValueType(0); shouldFoldConstantShiftPairToMask() local
3365 EVT VT = Y.getValueType(); shouldFoldMaskToVariableShiftPair() local
3395 MVT VT = MVT::getIntegerVT(NumBits); hasFastEqualityCompare() local
3657 getConstVector(ArrayRef<int> Values,MVT VT,SelectionDAG & DAG,const SDLoc & dl,bool IsMask=false) getConstVector() argument
3688 getConstVector(ArrayRef<APInt> Bits,const APInt & Undefs,MVT VT,SelectionDAG & DAG,const SDLoc & dl) getConstVector() argument
3728 getConstVector(ArrayRef<APInt> Bits,MVT VT,SelectionDAG & DAG,const SDLoc & dl) getConstVector() argument
3735 getZeroVector(MVT VT,const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl) getZeroVector() argument
3787 EVT VT = Vec.getValueType(); extractSubVector() local
3844 EVT VT = Vec.getValueType(); insertSubVector() local
3874 widenSubVector(MVT VT,SDValue Vec,bool ZeroNewElements,const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl) widenSubVector() argument
3896 MVT VT = MVT::getVectorVT(SVT, WideNumElts); widenSubVector() local
3902 widenMaskVectorType(MVT VT,const X86Subtarget & Subtarget) widenMaskVectorType() argument
3915 MVT VT = widenMaskVectorType(Vec.getSimpleValueType(), Subtarget); widenMaskVector() local
3935 EVT VT = Src.getValueType(); collectConcatOps() local
4004 EVT VT = Op.getValueType(); splitVector() local
4023 EVT VT = Op.getValueType(); splitVectorOp() local
4050 EVT VT = Op.getValueType(); splitVectorIntUnary() local
4065 EVT VT = Op.getValueType(); splitVectorIntBinary() local
4082 SplitOpsAndApply(SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & DL,EVT VT,ArrayRef<SDValue> Ops,F Builder,bool CheckBWI=true) SplitOpsAndApply() argument
4123 getAVX512Node(unsigned Opcode,const SDLoc & DL,MVT VT,ArrayRef<SDValue> Ops,SelectionDAG & DAG,const X86Subtarget & Subtarget) getAVX512Node() argument
4359 EVT VT = EVT::getVectorVT(*DAG.getContext(), SubSVT, 2 * SubNumElts); concatSubVectors() local
4367 getOnesVector(EVT VT,SelectionDAG & DAG,const SDLoc & dl) getOnesVector() argument
4377 getEXTEND_VECTOR_INREG(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue In,SelectionDAG & DAG) getEXTEND_VECTOR_INREG() argument
4403 getBitSelect(const SDLoc & DL,MVT VT,SDValue LHS,SDValue RHS,SDValue Mask,SelectionDAG & DAG) getBitSelect() argument
4410 createUnpackShuffleMask(EVT VT,SmallVectorImpl<int> & Mask,bool Lo,bool Unary) createUnpackShuffleMask() argument
4430 createSplat2ShuffleMask(MVT VT,SmallVectorImpl<int> & Mask,bool Lo) createSplat2ShuffleMask() argument
4442 getVectorShuffle(SelectionDAG & DAG,EVT VT,const SDLoc & dl,SDValue V1,SDValue V2,ArrayRef<int> Mask) getVectorShuffle() argument
4463 getUnpackl(SelectionDAG & DAG,const SDLoc & dl,EVT VT,SDValue V1,SDValue V2) getUnpackl() argument
4471 getUnpackh(SelectionDAG & DAG,const SDLoc & dl,EVT VT,SDValue V1,SDValue V2) getUnpackh() argument
4482 getPack(SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & dl,MVT VT,SDValue LHS,SDValue RHS,bool PackHiHalf=false) getPack() argument
4552 MVT VT = V2.getSimpleValueType(); getShuffleVectorZeroOrUndef() local
4604 EVT VT = Op.getValueType(); getTargetConstantBitsFromNode() local
5006 MVT VT = V.getSimpleValueType(); IsNOT() local
5027 createPackShuffleMask(MVT VT,SmallVectorImpl<int> & Mask,bool Unary,unsigned NumStages=1) createPackShuffleMask() argument
5049 getPackDemandedElts(EVT VT,const APInt & DemandedElts,APInt & DemandedLHS,APInt & DemandedRHS) getPackDemandedElts() argument
5074 getHorizDemandedElts(EVT VT,const APInt & DemandedElts,APInt & DemandedLHS,APInt & DemandedRHS) getHorizDemandedElts() argument
5108 getTargetShuffleMask(SDNode * N,MVT VT,bool AllowSentinelZero,SmallVectorImpl<SDValue> & Ops,SmallVectorImpl<int> & Mask,bool & IsUnary) getTargetShuffleMask() argument
5410 getTargetShuffleMask(SDNode * N,MVT VT,bool AllowSentinelZero,SmallVectorImpl<SDValue> & Ops,SmallVectorImpl<int> & Mask) getTargetShuffleMask() argument
5515 MVT VT = N.getSimpleValueType(); getTargetShuffleAndZeroables() local
5687 MVT VT = N.getSimpleValueType(); getFauxShuffleMask() local
6183 EVT VT = Op.getValueType(); getTargetShuffleInputs() local
6214 EVT VT = Op.getValueType(); getTargetShuffleInputs() local
6225 getBROADCAST_LOAD(unsigned Opcode,const SDLoc & DL,EVT VT,EVT MemVT,MemSDNode * Mem,unsigned Offset,SelectionDAG & DAG) getBROADCAST_LOAD() argument
6255 EVT VT = Op.getValueType(); getShuffleScalarElt() local
6356 MVT VT = Op.getSimpleValueType(); LowerBuildVectorAsInsert() local
6500 MVT VT = Op.getSimpleValueType(); LowerBuildVectorv4x32() local
6533 MVT VT = Elt.getOperand(0).getSimpleValueType(); LowerBuildVectorv4x32() local
6544 MVT VT = V1.getSimpleValueType(); LowerBuildVectorv4x32() local
6616 getVShift(bool isLeft,EVT VT,SDValue SrcOp,unsigned NumBits,SelectionDAG & DAG,const TargetLowering & TLI,const SDLoc & dl) getVShift() argument
6628 LowerAsSplatVectorLoad(SDValue SrcOp,MVT VT,const SDLoc & dl,SelectionDAG & DAG) LowerAsSplatVectorLoad() argument
6750 EltsFromConsecutiveLoads(EVT VT,ArrayRef<SDValue> Elts,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget,bool IsAfterLegalize) EltsFromConsecutiveLoads() argument
6857 __anon973982071502(EVT VT, LoadSDNode *LDBase) EltsFromConsecutiveLoads() argument
7032 combineToConsecutiveLoads(EVT VT,SDValue Op,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget,bool IsAfterLegalize) combineToConsecutiveLoads() argument
7049 getConstantVector(MVT VT,ArrayRef<APInt> Bits,const APInt & Undefs,LLVMContext & C) getConstantVector() argument
7074 getConstantVector(MVT VT,const APInt & SplatValue,unsigned SplatBitSize,LLVMContext & C) getConstantVector() argument
7141 MVT VT = BVOp->getSimpleValueType(0); lowerBuildVectorAsBroadcast() local
7404 MVT VT = Op.getSimpleValueType(); buildFromShuffleMostly() local
7478 MVT VT = Op.getSimpleValueType(); LowerBUILD_VECTORvXbf16() local
7493 MVT VT = Op.getSimpleValueType(); LowerBUILD_VECTORvXi1() local
7619 EVT VT = N->getValueType(0); isHorizontalBinOpPart() local
7733 MVT VT = V0.getSimpleValueType(); ExpandHorizontalBinOp() local
7776 MVT VT = BV->getSimpleValueType(0); isAddSubOrSubAdd() local
7935 MVT VT = BV->getSimpleValueType(0); lowerToAddSubOrFMAddSub() local
7968 MVT VT = BV->getSimpleValueType(0); isHopBuildVector() local
8058 MVT VT = BV->getSimpleValueType(0); getHopForBuildVector() local
8102 MVT VT = BV->getSimpleValueType(0); LowerToHorizontalOp() local
8218 MVT VT = Op->getSimpleValueType(0); lowerBuildVectorToBitOp() local
8295 MVT VT = Op.getSimpleValueType(); materializeVectorConstant() local
8317 createVariablePermute(MVT VT,SDValue SrcVec,SDValue IndicesVec,SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) createVariablePermute() argument
8454 EVT VT = Idx.getValueType(); createVariablePermute() local
8626 MVT VT = V.getSimpleValueType(); LowerBUILD_VECTORAsVariablePermute() local
8634 MVT VT = Op.getSimpleValueType(); LowerBUILD_VECTOR() local
9217 MVT VT = Op.getSimpleValueType(); LowerCONCAT_VECTORS() local
9280 is128BitLaneCrossingShuffleMask(MVT VT,ArrayRef<int> Mask) is128BitLaneCrossingShuffleMask() argument
9324 isRepeatedShuffleMask(unsigned LaneSizeInBits,MVT VT,ArrayRef<int> Mask,SmallVectorImpl<int> & RepeatedMask) isRepeatedShuffleMask() argument
9354 is128BitLaneRepeatedShuffleMask(MVT VT,ArrayRef<int> Mask,SmallVectorImpl<int> & RepeatedMask) is128BitLaneRepeatedShuffleMask() argument
9360 is128BitLaneRepeatedShuffleMask(MVT VT,ArrayRef<int> Mask) is128BitLaneRepeatedShuffleMask() argument
9367 is256BitLaneRepeatedShuffleMask(MVT VT,ArrayRef<int> Mask,SmallVectorImpl<int> & RepeatedMask) is256BitLaneRepeatedShuffleMask() argument
9411 isRepeatedTargetShuffleMask(unsigned LaneSizeInBits,MVT VT,ArrayRef<int> Mask,SmallVectorImpl<int> & RepeatedMask) isRepeatedTargetShuffleMask() argument
9451 MVT VT = Op.getSimpleValueType(); IsElementEquivalent() local
9512 isTargetShuffleEquivalent(MVT VT,ArrayRef<int> Mask,ArrayRef<int> ExpectedMask,const SelectionDAG & DAG,SDValue V1=SDValue (),SDValue V2=SDValue ()) isTargetShuffleEquivalent() argument
9573 isUnpackWdShuffleMask(ArrayRef<int> Mask,MVT VT,const SelectionDAG & DAG) isUnpackWdShuffleMask() argument
9593 MVT VT = MVT::getVectorVT(EltVT, Mask.size()); is128BitUnpackShuffleMask() local
9694 lowerShuffleWithPSHUFB(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithPSHUFB() argument
9752 lowerShuffleToEXPAND(const SDLoc & DL,MVT VT,const APInt & Zeroable,ArrayRef<int> Mask,SDValue & V1,SDValue & V2,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerShuffleToEXPAND() argument
9775 matchShuffleWithUNPCK(MVT VT,SDValue & V1,SDValue & V2,unsigned & UnpackOpcode,bool IsUnary,ArrayRef<int> TargetMask,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) matchShuffleWithUNPCK() argument
9864 lowerShuffleWithUNPCK(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,SelectionDAG & DAG) lowerShuffleWithUNPCK() argument
9891 lowerShuffleWithUNPCK256(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,SelectionDAG & DAG) lowerShuffleWithUNPCK256() argument
9917 matchShuffleAsVTRUNC(MVT & SrcVT,MVT & DstVT,MVT VT,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget) matchShuffleAsVTRUNC() argument
10016 lowerShuffleWithVPMOV(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithVPMOV() argument
10066 lowerShuffleAsVTRUNC(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsVTRUNC() argument
10220 matchShuffleWithPACK(MVT VT,MVT & SrcVT,SDValue & V1,SDValue & V2,unsigned & PackOpcode,ArrayRef<int> TargetMask,const SelectionDAG & DAG,const X86Subtarget & Subtarget,unsigned MaxStages=1) matchShuffleWithPACK() argument
10291 lowerShuffleWithPACK(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerShuffleWithPACK() argument
10340 lowerShuffleAsBitMask(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsBitMask() argument
10396 lowerShuffleAsBitBlend(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG) lowerShuffleAsBitBlend() argument
10419 matchShuffleAsBlend(MVT VT,SDValue V1,SDValue V2,MutableArrayRef<int> Mask,const APInt & Zeroable,bool & ForceV1Zero,bool & ForceV2Zero,uint64_t & BlendMask) matchShuffleAsBlend() argument
10512 lowerShuffleAsBlend(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Original,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsBlend() argument
10673 lowerShuffleAsBlendAndPermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG,bool ImmBlends=false) lowerShuffleAsBlendAndPermute() argument
10712 lowerShuffleAsUNPCKAndPermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG) lowerShuffleAsUNPCKAndPermute() argument
10795 lowerShuffleAsPermuteAndUnpack(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsPermuteAndUnpack() argument
10907 lowerShuffleAsByteRotateAndPermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsByteRotateAndPermute() argument
11024 lowerShuffleAsDecomposedShuffleMerge(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsDecomposedShuffleMerge() argument
11161 lowerShuffleAsBitRotate(const SDLoc & DL,MVT VT,SDValue V1,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsBitRotate() argument
11290 matchShuffleAsByteRotate(MVT VT,SDValue & V1,SDValue & V2,ArrayRef<int> Mask) matchShuffleAsByteRotate() argument
11312 lowerShuffleAsByteRotate(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsByteRotate() argument
11369 lowerShuffleAsVALIGN(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsVALIGN() argument
11420 lowerShuffleAsByteShiftMask(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsByteShiftMask() argument
11569 lowerShuffleAsShift(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG,bool BitwiseOnly) lowerShuffleAsShift() argument
11608 matchShuffleAsEXTRQ(MVT VT,SDValue & V1,SDValue & V2,ArrayRef<int> Mask,uint64_t & BitLen,uint64_t & BitIdx,const APInt & Zeroable) matchShuffleAsEXTRQ() argument
11664 matchShuffleAsINSERTQ(MVT VT,SDValue & V1,SDValue & V2,ArrayRef<int> Mask,uint64_t & BitLen,uint64_t & BitIdx) matchShuffleAsINSERTQ() argument
11730 lowerShuffleWithSSE4A(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,SelectionDAG & DAG) lowerShuffleWithSSE4A() argument
11758 lowerShuffleAsSpecificZeroOrAnyExtend(const SDLoc & DL,MVT VT,int Scale,int Offset,bool AnyExt,SDValue InputV,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsSpecificZeroOrAnyExtend() argument
11922 lowerShuffleAsZeroOrAnyExtend(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsZeroOrAnyExtend() argument
12042 MVT VT = V.getSimpleValueType(); getScalarValueForVectorElement() local
12074 isSoftF16(T VT,const X86Subtarget & Subtarget) isSoftF16() argument
12084 lowerShuffleAsElementInsertion(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsElementInsertion() argument
12209 lowerShuffleAsTruncBroadcast(const SDLoc & DL,MVT VT,SDValue V0,int BroadcastIdx,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsTruncBroadcast() argument
12301 MVT VT = N0.getSimpleValueType(); lowerShuffleOfExtractsAsVperm() local
12352 lowerShuffleAsBroadcast(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsBroadcast() argument
12841 lowerShuffleWithSHUFPS(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,SelectionDAG & DAG) lowerShuffleWithSHUFPS() argument
13179 lowerV8I16GeneralSingleInputShuffle(const SDLoc & DL,MVT VT,SDValue V,MutableArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8I16GeneralSingleInputShuffle() argument
13673 lowerShuffleAsBlendOfPSHUFBs(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,SelectionDAG & DAG,bool & V1InUse,bool & V2InUse) lowerShuffleAsBlendOfPSHUFBs() argument
13970 lowerShuffleWithPERMV(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithPERMV() argument
14371 lower128BitShuffle(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower128BitShuffle() argument
14408 splitAndLowerShuffle(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG,bool SimpleOnly) splitAndLowerShuffle() argument
14537 lowerShuffleAsSplitOrBlend(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsSplitOrBlend() argument
14591 lowerShuffleAsLanePermuteAndSHUFP(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG) lowerShuffleAsLanePermuteAndSHUFP() argument
14628 lowerShuffleAsLanePermuteAndPermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerShuffleAsLanePermuteAndPermute() argument
14751 lowerShuffleAsLanePermuteAndShuffle(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerShuffleAsLanePermuteAndShuffle() argument
14809 lowerV2X128Shuffle(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV2X128Shuffle() argument
14930 lowerShuffleAsLanePermuteAndRepeatedMask(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsLanePermuteAndRepeatedMask() argument
15160 MVT VT = V1.getSimpleValueType(); getShuffleHalfVectors() local
15193 lowerShuffleWithUndefHalf(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithUndefHalf() argument
15305 lowerShuffleAsRepeatedMaskAndLanePermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsRepeatedMaskAndLanePermute() argument
15503 matchShuffleWithSHUFPD(MVT VT,SDValue & V1,SDValue & V2,bool & ForceV1Zero,bool & ForceV2Zero,unsigned & ShuffleImm,ArrayRef<int> Mask,const APInt & Zeroable) matchShuffleWithSHUFPD() argument
15548 lowerShuffleWithSHUFPD(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithSHUFPD() argument
15575 lowerShuffleAsVTRUNCAndUnpack(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,SelectionDAG & DAG) lowerShuffleAsVTRUNCAndUnpack() argument
15623 lowerShufflePairAsUNPCKAndPermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG) lowerShufflePairAsUNPCKAndPermute() argument
16438 lower256BitShuffle(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower256BitShuffle() argument
16510 lowerV4X128Shuffle(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV4X128Shuffle() argument
17070 lower512BitShuffle(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower512BitShuffle() argument
17144 lower1BitShuffleAsKSHIFTR(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower1BitShuffleAsKSHIFTR() argument
17219 lower1BitShuffle(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower1BitShuffle() argument
17428 MVT VT = V.getSimpleValueType().getScalarType(); canCombineAsMaskOperation() local
17491 MVT VT = Op.getSimpleValueType(); lowerVECTOR_SHUFFLE() local
17633 MVT VT = Op.getSimpleValueType(); lowerVSELECTtoVectorShuffle() local
17652 MVT VT = Op.getSimpleValueType(); LowerVSELECT() local
17744 MVT VT = Op.getSimpleValueType(); LowerEXTRACT_VECTOR_ELT_SSE4() local
17841 MVT VT = N->getSimpleValueType(0); getExtractedDemandedElts() local
17940 MVT VT = Op.getSimpleValueType(); LowerEXTRACT_VECTOR_ELT() local
18057 MVT VT = Op.getSimpleValueType(); LowerINSERT_VECTOR_ELT() local
18838 MVT VT = Op.getSimpleValueType(); LowerI64IntToFP_AVX512DQ() local
18879 MVT VT = Op.getSimpleValueType(); LowerI64IntToFP16() local
18976 MVT VT = CastToFP.getSimpleValueType(); lowerFPToIntToFP() local
19023 MVT VT = Op->getSimpleValueType(0); lowerINT_TO_FP_vXi64() local
19112 MVT VT = Op.getSimpleValueType(); promoteXINT_TO_FP() local
19127 isLegalConversion(MVT VT,bool IsSigned,const X86Subtarget & Subtarget) isLegalConversion() argument
19154 MVT VT = Op.getSimpleValueType(); LowerSINT_TO_FP() local
19480 MVT VT = Op->getSimpleValueType(0); lowerUINT_TO_FP_vXi32() local
19963 MVT VT = Op.getSimpleValueType(); LowerAVXExtend() local
20024 SplitAndExtendv16i1(unsigned ExtOpc,MVT VT,SDValue In,const SDLoc & dl,SelectionDAG & DAG) SplitAndExtendv16i1() argument
20040 MVT VT = Op->getSimpleValueType(0); LowerZERO_EXTEND_Mask() local
20433 MVT VT = Op.getSimpleValueType(); LowerTruncateVecI1() local
20512 MVT VT = Op.getSimpleValueType(); LowerTRUNCATE() local
20634 expandFP_TO_UINT_SSE(MVT VT,SDValue Src,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) expandFP_TO_UINT_SSE() argument
20674 MVT VT = Op->getSimpleValueType(0); LowerFP_TO_INT() local
21244 MVT VT = Op.getSimpleValueType(); LowerFP_EXTEND() local
21380 MVT VT = Op.getSimpleValueType(); LowerFP_ROUND() local
21636 MVT VT = Op.getSimpleValueType(); LowerFROUND() local
21669 MVT VT = Op.getSimpleValueType(); LowerFABSorFNEG() local
21722 MVT VT = Op.getSimpleValueType(); LowerFCOPYSIGN() local
21788 MVT VT = Op.getSimpleValueType(); LowerFGETSIGN() local
21892 combineVectorSizedSetCCEquality(EVT VT,SDValue X,SDValue Y,ISD::CondCode CC,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineVectorSizedSetCCEquality() argument
22048 EVT VT = MVT::Other; matchScalarReduction() local
22116 EVT VT = LHS.getValueType(); LowerVectorAllEqual() local
22305 EVT VT = VecIns[0].getValueType(); MatchVectorAllEqualTest() local
22628 EVT VT = Op.getValueType(); isFsqrtCheap() local
22651 EVT VT = Op.getValueType(); getSqrtEstimate() local
22703 EVT VT = Op.getValueType(); getRecipEstimate() local
22775 EVT VT = N->getValueType(0); BuildSDIVPow2() local
22926 splitIntVSETCC(EVT VT,SDValue LHS,SDValue RHS,ISD::CondCode Cond,SelectionDAG & DAG,const SDLoc & dl) splitIntVSETCC() argument
22955 MVT VT = Op.getSimpleValueType(); LowerIntVSETCC_AVX512() local
22982 MVT VT = V.getSimpleValueType(); incDecVectorConstant() local
23010 LowerVSETCCWithSUBUS(SDValue Op0,SDValue Op1,MVT VT,ISD::CondCode Cond,const SDLoc & dl,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVSETCCWithSUBUS() argument
23072 MVT VT = Op->getSimpleValueType(0); LowerVSETCC() local
23510 MVT VT = Op0.getSimpleValueType(); EmitAVX512Test() local
23633 MVT VT = Op->getSimpleValueType(0); LowerSETCC() local
23835 MVT VT = Op1.getSimpleValueType(); LowerSELECT() local
24144 MVT VT = Op->getSimpleValueType(0); LowerSIGN_EXTEND_Mask() local
24218 MVT VT = Op->getSimpleValueType(0); LowerEXTEND_VECTOR_INREG() local
24339 MVT VT = Op->getSimpleValueType(0); LowerSIGN_EXTEND() local
24730 EVT VT = Node->getValueType(0); LowerDYNAMIC_STACKALLOC() local
24970 getTargetVShiftByConstNode(unsigned Opc,const SDLoc & dl,MVT VT,SDValue SrcOp,uint64_t ShiftAmt,SelectionDAG & DAG) getTargetVShiftByConstNode() argument
25022 getTargetVShiftNode(unsigned Opc,const SDLoc & dl,MVT VT,SDValue SrcOp,SDValue ShAmt,int ShAmtIdx,const X86Subtarget & Subtarget,SelectionDAG & DAG) getTargetVShiftNode() argument
25157 MVT VT = Op.getSimpleValueType(); getVectorMaskingNode() local
25188 MVT VT = Op.getSimpleValueType(); getScalarMaskingNode() local
25306 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_WO_CHAIN() local
25635 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_WO_CHAIN() local
26323 MVT VT = Op.getSimpleValueType(); getGatherNode() local
26782 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_W_CHAIN() local
26801 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_W_CHAIN() local
26847 MVT VT = Op2.getSimpleValueType(); LowerINTRINSIC_W_CHAIN() local
26883 MVT VT = Op2.getSimpleValueType(); LowerINTRINSIC_W_CHAIN() local
27100 EVT VT = Op.getValueType(); LowerFRAMEADDR() local
27135 getRegisterByName(const char * RegName,LLT VT,const MachineFunction & MF) const getRegisterByName() argument
27426 MVT VT = Op.getSimpleValueType(); LowerGET_ROUNDING() local
27703 MVT VT = Op.getSimpleValueType(); LowerVectorCTLZ_AVX512CDI() local
27732 MVT VT = Op.getSimpleValueType(); LowerVectorCTLZInRegLUT() local
27814 MVT VT = Op.getSimpleValueType(); LowerVectorCTLZ() local
27835 MVT VT = Op.getSimpleValueType(); LowerCTLZ() local
27874 MVT VT = Op.getSimpleValueType(); LowerCTTZ() local
27899 MVT VT = Op.getSimpleValueType(); lowerAddSub() local
27914 MVT VT = Op.getSimpleValueType(); LowerADDSAT_SUBSAT() local
27984 MVT VT = Op.getSimpleValueType(); LowerABS() local
28021 MVT VT = Op.getSimpleValueType(); LowerAVG() local
28036 MVT VT = Op.getSimpleValueType(); LowerMINMAX() local
28054 EVT VT = Op.getValueType(); LowerFMINIMUM_FMAXIMUM() local
28199 MVT VT = Op.getSimpleValueType(); LowerABD() local
28247 MVT VT = Op.getSimpleValueType(); LowerMUL() local
28388 LowervXi8MulWithUNPCK(SDValue A,SDValue B,const SDLoc & dl,MVT VT,bool IsSigned,const X86Subtarget & Subtarget,SelectionDAG & DAG,SDValue * Low=nullptr) LowervXi8MulWithUNPCK() argument
28469 MVT VT = Op.getSimpleValueType(); LowerMULH() local
28575 MVT VT = Op.getSimpleValueType(); LowerMULO() local
28706 EVT VT = Op.getValueType(); LowerWin64_i128OP() local
28771 EVT VT = Op.getValueType(); LowerWin64_FP_TO_INT128() local
28804 EVT VT = Op.getValueType(); LowerWin64_INT128_TO_FP() local
28840 supportedVectorShiftWithImm(EVT VT,const X86Subtarget & Subtarget,unsigned Opcode) supportedVectorShiftWithImm() argument
28866 supportedVectorShiftWithBaseAmnt(EVT VT,const X86Subtarget & Subtarget,unsigned Opcode) supportedVectorShiftWithBaseAmnt() argument
28873 supportedVectorVarShift(EVT VT,const X86Subtarget & Subtarget,unsigned Opcode) supportedVectorVarShift() argument
28899 MVT VT = Op.getSimpleValueType(); LowerShiftByScalarImmediate() local
29044 MVT VT = Op.getSimpleValueType(); LowerShiftByScalarVariable() local
29109 MVT VT = Amt.getSimpleValueType(); convertShiftLeftToScale() local
29163 MVT VT = Op.getSimpleValueType(); LowerShift() local
29650 MVT VT = Op.getSimpleValueType(); LowerFunnelShift() local
29827 MVT VT = Op.getSimpleValueType(); LowerRotate() local
30866 LowerHorizontalByteSum(SDValue V,MVT VT,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerHorizontalByteSum() argument
30933 MVT VT = Op.getSimpleValueType(); LowerVectorCTPOPInRegLUT() local
30979 MVT VT = Op.getSimpleValueType(); LowerVectorCTPOP() local
31029 MVT VT = Op.getSimpleValueType(); LowerBITREVERSE_XOP() local
31075 MVT VT = Op.getSimpleValueType(); LowerBITREVERSE() local
31142 MVT VT = Op.getSimpleValueType(); LowerPARITY() local
31233 MVT VT = N->getSimpleValueType(0); lowerAtomicArith() local
31299 EVT VT = Node->getMemoryVT(); LowerATOMIC_STORE() local
31372 MVT VT = N->getSimpleValueType(0); LowerADDSUBO_CARRY() local
31514 MVT VT = Src.getSimpleValueType(); LowerMSCATTER() local
31574 MVT VT = Op.getSimpleValueType(); LowerMLOAD() local
31640 MVT VT = DataToStore.getSimpleValueType(); LowerMSTORE() local
31685 MVT VT = Op.getSimpleValueType(); LowerMGATHER() local
31774 EVT VT = Op.getValueType(); LowerCVTPS2PH() local
32022 EVT VT = N->getValueType(0); ReplaceNodeResults() local
32034 EVT VT = N->getValueType(0); ReplaceNodeResults() local
32074 EVT VT = N->getValueType(0); ReplaceNodeResults() local
32093 EVT VT = N->getValueType(0); ReplaceNodeResults() local
32132 EVT VT = N->getValueType(0); ReplaceNodeResults() local
32162 EVT VT = N->getValueType(0); ReplaceNodeResults() local
32176 EVT VT = N->getValueType(0); ReplaceNodeResults() local
32202 MVT VT = N->getSimpleValueType(0); ReplaceNodeResults() local
32303 EVT VT = N->getValueType(0); ReplaceNodeResults() local
32380 EVT VT = N->getValueType(0); ReplaceNodeResults() local
32630 EVT VT = N->getValueType(0); ReplaceNodeResults() local
32759 EVT VT = N->getValueType(0); ReplaceNodeResults() local
33027 EVT VT = N->getValueType(0); ReplaceNodeResults() local
33064 MVT VT = N->getSimpleValueType(0); ReplaceNodeResults() local
36445 EVT VT = Op.getValueType(); targetShrinkDemandedConstant() local
36540 EVT VT = Op.getValueType(); computeKnownBitsForTargetNode() local
36882 EVT VT = Op.getValueType(); ComputeNumSignBitsForTargetNode() local
37056 narrowLoadToVZLoad(LoadSDNode * LN,MVT MemVT,MVT VT,SelectionDAG & DAG) narrowLoadToVZLoad() argument
37765 __anon973982077802(MVT VT, SDValue Op) combineX86ShuffleChain() argument
38830 MVT VT = Root.getSimpleValueType(); combineX86ShufflesConstants() local
38970 EVT VT = Op.getValueType(); combineX86ShufflesRecursively() local
39397 MVT VT = N.getSimpleValueType(); getPSHUFShuffleMask() local
39569 combineCommutableSHUFP(SDValue N,MVT VT,const SDLoc & DL,SelectionDAG & DAG) combineCommutableSHUFP() argument
39795 MVT VT = V.getSimpleValueType(); canonicalizeLaneShuffleWithRepeatedOps() local
39846 MVT VT = N.getSimpleValueType(); combineTargetShuffle() local
40626 EVT VT = N->getValueType(0); isAddSubOrSubAdd() local
40691 MVT VT = N->getSimpleValueType(0); combineShuffleToFMAddSub() local
40736 MVT VT = N->getSimpleValueType(0); combineShuffleToAddSubOrFMAddSub() local
40772 EVT VT = N->getValueType(0); combineShuffleOfConcatUndef() local
40813 EVT VT = Shuf->getValueType(0); narrowShuffle() local
40852 EVT VT = N->getValueType(0); combineShuffle() local
40976 EVT VT = Op.getValueType(); SimplifyDemandedVectorEltsForTargetNode() local
41716 EVT VT = Op.getValueType(); SimplifyDemandedBitsForTargetNode() local
42223 EVT VT = Op.getValueType(); SimplifyMultipleUseDemandedBitsForTargetNode() local
42501 combineBitcastvxi1(SelectionDAG & DAG,EVT VT,SDValue Src,const SDLoc & DL,const X86Subtarget & Subtarget) combineBitcastvxi1() argument
42803 combineBitcastToBoolVector(EVT VT,SDValue V,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineBitcastToBoolVector() argument
42875 EVT VT = N->getValueType(0); combineBitcast() local
43243 MVT VT = MVT::getVectorVT(MVT::i32, Ops[0].getValueSizeInBits() / 32); createVPDPBUSD() local
43275 MVT VT = MVT::getVectorVT(MVT::i64, Ops[0].getValueSizeInBits() / 64); createPSADBW() local
43510 EVT VT = Extract->getOperand(0).getValueType(); combineVPDPBUSDPattern() local
43582 EVT VT = Extract->getOperand(0).getValueType(); combineBasicSADPattern() local
43656 EVT VT = N->getValueType(0); combineExtractWithShuffle() local
43850 EVT VT = ExtElt->getValueType(0); scalarizeExtEltFP() local
43964 EVT VT = ExtElt->getValueType(0); combineArithReduction() local
44079 MVT VT = MVT::getVectorVT(MVT::i64, Ops[0].getValueSizeInBits() / 64); combineArithReduction() local
44150 EVT VT = N->getValueType(0); combineExtractVectorElt() local
44328 combineToExtendBoolVectorInReg(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N0,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineToExtendBoolVectorInReg() argument
44433 EVT VT = LHS.getValueType(); combineVSelectWithAllOnesOrZeros() local
44540 EVT VT = N->getValueType(0); narrowVectorSelect() local
44573 EVT VT = N->getValueType(0); combineSelectOfTwoConstants() local
44649 EVT VT = N->getValueType(0); combineVSelectToBLENDV() local
44746 combineLogicBlendIntoConditionalNegate(EVT VT,SDValue Mask,SDValue X,SDValue Y,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineLogicBlendIntoConditionalNegate() argument
44843 EVT VT = LHS.getValueType(); combineSelect() local
45705 MVT VT = EFLAGS.getSimpleValueType(); combinePTESTCC() local
46357 EVT VT = N->getValueType(0); combineCMov() local
46374 EVT VT = N->getOperand(0).getValueType(); canReduceVMulWidth() local
46457 EVT VT = N->getOperand(0).getValueType(); reduceVMULWidth() local
46506 combineMulSpecial(uint64_t MulAmt,SDNode * N,SelectionDAG & DAG,EVT VT,const SDLoc & DL) combineMulSpecial() argument
46602 EVT VT = N->getValueType(0); combineMulToPMADDWD() local
46711 EVT VT = N->getValueType(0); combineMulToPMULDQ() local
46751 EVT VT = N->getValueType(0); combineMul() local
46954 EVT VT = N->getValueType(0); combineShiftToPMULH() local
46992 EVT VT = N0.getValueType(); combineShiftLeft() local
47037 EVT VT = N0.getValueType(); combineShiftRightArithmetic() local
47097 EVT VT = N0.getValueType(); combineShiftRightLogical() local
47151 EVT VT = N->getValueType(0); combineHorizOpWithShuffle() local
47296 EVT VT = N->getValueType(0); combineVectorPack() local
47448 MVT VT = N->getSimpleValueType(0); combineVectorHADDSUB() local
47494 EVT VT = N->getValueType(0); combineVectorShiftVar() local
47527 EVT VT = N->getValueType(0); combineVectorShiftImm() local
47673 EVT VT = N->getValueType(0); combineVectorInsert() local
47729 EVT VT = CMP00.getValueType(); combineCompareEqual() local
47819 MVT VT = N->getSimpleValueType(0); combineAndNotIntoANDNP() local
47851 EVT VT = N->getValueType(0); combineAndShuffleNot() local
47933 PromoteMaskArithmetic(SDNode * N,EVT VT,SelectionDAG & DAG,unsigned Depth) PromoteMaskArithmetic() argument
47991 EVT VT = N->getValueType(0); PromoteMaskArithmetic() local
48035 EVT VT = N->getValueType(0); convertIntLogicToFPLogic() local
48138 EVT VT = N->getValueType(0); combineBitOpWithShift() local
48181 EVT VT = N->getValueType(0); combineBitOpWithPACK() local
48221 EVT VT = Op0.getValueType(); combineAndMaskToShift() local
48297 hasBZHI(const X86Subtarget & Subtarget,MVT VT) hasBZHI() argument
48320 MVT VT = Node->getSimpleValueType(0); combineAndLoadToBZHI() local
48404 EVT VT = N->getValueType(0); combineScalarAndWithMaskSetcc() local
48527 EVT VT = N->getValueType(0); combineBMILogicOp() local
48549 EVT VT = N->getValueType(0); combineAnd() local
48812 MVT VT = N->getSimpleValueType(0); canonicalizeBitSelect() local
48914 EVT VT = N->getValueType(0); combineLogicBlendIntoPBLENDV() local
48967 EVT VT = Cmp.getOperand(0).getValueType(); lowerX86CmpEqZeroToCtlzSrl() local
49074 EVT VT = And1_L->getValueType(0); foldMaskedMergeImpl() local
49118 combineAddOrSubToADCOrSBB(bool IsSub,const SDLoc & DL,EVT VT,SDValue X,SDValue Y,SelectionDAG & DAG,bool ZeroSecondOpOnly=false) combineAddOrSubToADCOrSBB() argument
49306 EVT VT = N->getValueType(0); combineAddOrSubToADCOrSBB() local
49341 EVT VT = N->getValueType(0); combineOrXorWithSETCC() local
49356 EVT VT = N->getValueType(0); combineOr() local
49568 EVT VT = N->getValueType(0); foldVectorXorShiftIntoCmp() local
49620 detectUSatPattern(SDValue In,EVT VT,SelectionDAG & DAG,const SDLoc & DL) detectUSatPattern() argument
49667 detectSSatPattern(SDValue In,EVT VT,bool MatchPackUS=false) detectSSatPattern() argument
49701 combineTruncateWithSat(SDValue In,EVT VT,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineTruncateWithSat() argument
49804 detectAVGPattern(SDValue In,EVT VT,SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & DL) detectAVGPattern() argument
50180 EVT VT = ML->getValueType(0); reduceMaskedLoadToScalarLoad() local
50211 EVT VT = ML->getValueType(0); combineMaskedLoadConstantMask() local
50276 EVT VT = Mld->getValueType(0); combineMaskedLoad() local
50315 EVT VT = Value.getValueType(); reduceMaskedStoreToScalarStore() local
50338 EVT VT = Mst->getValue().getValueType(); combineMaskedStore() local
50386 EVT VT = StoredVal.getValueType(); combineStore() local
50667 MVT VT = StoredVal.getSimpleValueType(); combineVEXTRACT_STORE() local
50714 MVT VT = LHS.getSimpleValueType(); isHorizontalBinOp() local
50887 EVT VT = N->getValueType(0); combineToHorizontalAddSub() local
50952 EVT VT = N->getValueType(0); combineFMulcFCMulc() local
51013 EVT VT = N->getValueType(0); combineFaddCFmul() local
51090 EVT VT = N->getValueType(0); combineTruncatedArithmetic() local
51163 combinePMULH(SDValue Src,EVT VT,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combinePMULH() argument
51247 detectPMADDUBSW(SDValue In,EVT VT,SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & DL) detectPMADDUBSW() argument
51380 EVT VT = N->getValueType(0); combineTruncate() local
51417 EVT VT = N->getValueType(0); combineVTRUNC() local
51454 EVT VT = Op->getValueType(0); isFNEG() local
51592 EVT VT = Arg.getValueType(); combineFneg() local
51631 EVT VT = Op.getValueType(); getNegatedExpression() local
51689 MVT VT = N->getSimpleValueType(0); lowerX86FPLogicOp() local
51737 EVT VT = N->getValueType(0); combineXorSubCTLZ() local
51792 EVT VT = N->getValueType(0); combineXor() local
51881 EVT VT = N->getValueType(0); combineBITREVERSE() local
51907 EVT VT = N->getValueType(0); combineBEXTR() local
51946 EVT VT = N->getValueType(0); combineFAndFNotToFAndn() local
52048 EVT VT = N->getValueType(0); combineFMinNumFMaxNum() local
52114 EVT VT = N->getValueType(0); combineX86INT_TO_FP() local
52148 EVT VT = N->getValueType(0); combineCVTP2I_CVTTP2I() local
52187 MVT VT = N->getSimpleValueType(0); combineAndnp() local
52421 EVT VT = N->getValueType(0); combineSignExtendInReg() local
52468 EVT VT = Ext->getValueType(0); promoteExtBeforeAdd() local
52545 EVT VT = CMovN.getValueType(); combineToExtendCMOV() local
52586 EVT VT = N->getValueType(0); combineExtSetcc() local
52631 EVT VT = N->getValueType(0); combineSext() local
52697 EVT VT = V.getValueType(); getInvertedVectorForFMA() local
52735 EVT VT = N->getValueType(0); combineFMA() local
52822 EVT VT = N->getValueType(0); combineFMADDSUB() local
52847 EVT VT = N->getValueType(0); combineZext() local
52907 truncateAVX512SetCCNoBWI(EVT VT,EVT OpVT,SDValue LHS,SDValue RHS,ISD::CondCode CC,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) truncateAVX512SetCCNoBWI() argument
52927 EVT VT = N->getValueType(0); combineSetCC() local
53156 MVT VT = N->getSimpleValueType(0); combineMOVMSK() local
53269 MVT VT = N->getSimpleValueType(0); combineTESTP() local
53481 EVT VT = N->getValueType(0); combineVectorCompareAndMaskUnaryOp() local
53562 EVT VT = N->getValueType(0); combineUIntToFP() local
53632 EVT VT = N->getValueType(0); combineSIntToFP() local
53814 EVT VT = Op.getValueType(); combineCMP() local
53952 MVT VT = LHS.getSimpleValueType(); combineX86AddSub() local
53988 MVT VT = N->getSimpleValueType(0); combineSBB() local
54025 EVT VT = N->getValueType(0); combineADC() local
54047 MVT VT = N->getSimpleValueType(0); combineADC() local
54063 matchPMADDWD(SelectionDAG & DAG,SDValue Op0,SDValue Op1,const SDLoc & DL,EVT VT,const X86Subtarget & Subtarget) matchPMADDWD() argument
54171 matchPMADDWD_2(SelectionDAG & DAG,SDValue N0,SDValue N1,const SDLoc & DL,EVT VT,const X86Subtarget & Subtarget) matchPMADDWD_2() argument
54311 combineAddOfPMADDWD(SelectionDAG & DAG,SDValue N0,SDValue N1,const SDLoc & DL,EVT VT) combineAddOfPMADDWD() argument
54385 EVT VT = N->getValueType(0); pushAddIntoCmovOfConsts() local
54422 EVT VT = N->getValueType(0); combineAdd() local
54508 MVT VT = N->getSimpleValueType(0); combineSubABS() local
54523 EVT VT = N->getValueType(0); combineSubSetcc() local
54567 EVT VT = Op0.getValueType(); combineSub() local
54612 MVT VT = N->getSimpleValueType(0); combineVectorCompare() local
54628 combineConcatVectorOps(const SDLoc & DL,MVT VT,ArrayRef<SDValue> Ops,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineConcatVectorOps() argument
54727 __anon97398207dc02(EVT VT, ArrayRef<SDValue> SubOps, unsigned I) combineConcatVectorOps() argument
54733 __anon97398207dd02(MVT VT, ArrayRef<SDValue> SubOps, unsigned Op) combineConcatVectorOps() argument
55228 EVT VT = N->getValueType(0); combineCONCAT_VECTORS() local
55430 MVT VT = Ext->getSimpleValueType(0); narrowExtractedVectorSelect() local
55488 MVT VT = N->getSimpleValueType(0); combineEXTRACT_SUBVECTOR() local
55664 EVT VT = N->getValueType(0); combineScalarToVector() local
55801 EVT VT = N->getValueType(0); combineVPMADD() local
55822 EVT VT = N->getValueType(0); combineEXTEND_VECTOR_INREG() local
55889 EVT VT = N->getValueType(0); combineKSHIFT() local
55936 EVT VT = N->getValueType(0); combineFP_EXTEND() local
56016 EVT VT = N->getSimpleValueType(0); combineBROADCAST_LOAD() local
56044 EVT VT = N->getValueType(0); combineFP_ROUND() local
56348 preferSextInRegOfTruncate(EVT TruncVT,EVT VT,EVT ExtVT) const preferSextInRegOfTruncate() argument
56421 EVT VT = LogicOp->getValueType(0); isDesirableToCombineLogicOpOfSETCC() local
56441 EVT VT = Op.getValueType(); IsDesirableToPromoteOp() local
57574 isIntDivCheap(EVT VT,AttributeList Attr) const isIntDivCheap() argument
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp228 getFPLibCall(EVT VT,RTLIB::Libcall Call_F32,RTLIB::Libcall Call_F64,RTLIB::Libcall Call_F80,RTLIB::Libcall Call_F128,RTLIB::Libcall Call_PPCF128) getFPLibCall() argument
569 getOUTLINE_ATOMIC(unsigned Opc,AtomicOrdering Order,MVT VT) getOUTLINE_ATOMIC() argument
610 getSYNC(unsigned Opc,MVT VT) getSYNC() argument
807 for (MVT VT : MVT::fp_valuetypes()) { initActions() local
816 for (MVT VT : MVT::all_valuetypes()) { initActions() local
1145 getVectorTypeBreakdownMVT(MVT VT,MVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT,TargetLoweringBase * TLI) getVectorTypeBreakdownMVT() argument
1459 MVT VT = (MVT::SimpleValueType) i; computeRegisterProperties() local
1598 getVectorTypeBreakdown(LLVMContext & Context,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) const getVectorTypeBreakdown() argument
1728 EVT VT = ValueVTs[j]; GetReturnInfo() local
1776 allowsMemoryAccessForAlignment(LLVMContext & Context,const DataLayout & DL,EVT VT,unsigned AddrSpace,Align Alignment,MachineMemOperand::Flags Flags,unsigned * Fast) const allowsMemoryAccessForAlignment() argument
1796 allowsMemoryAccessForAlignment(LLVMContext & Context,const DataLayout & DL,EVT VT,const MachineMemOperand & MMO,unsigned * Fast) const allowsMemoryAccessForAlignment() argument
1803 allowsMemoryAccess(LLVMContext & Context,const DataLayout & DL,EVT VT,unsigned AddrSpace,Align Alignment,MachineMemOperand::Flags Flags,unsigned * Fast) const allowsMemoryAccess() argument
1812 allowsMemoryAccess(LLVMContext & Context,const DataLayout & DL,EVT VT,const MachineMemOperand & MMO,unsigned * Fast) const allowsMemoryAccess() argument
1823 EVT VT = getApproximateEVTForLLT(Ty, DL, Context); allowsMemoryAccess() local
2095 getReciprocalOpName(bool IsSqrt,EVT VT) getReciprocalOpName() argument
2140 getOpEnabled(bool IsSqrt,EVT VT,StringRef Override) getOpEnabled() argument
2200 getOpRefinementSteps(bool IsSqrt,EVT VT,StringRef Override) getOpRefinementSteps() argument
2246 getRecipEstimateSqrtEnabled(EVT VT,MachineFunction & MF) const getRecipEstimateSqrtEnabled() argument
2251 getRecipEstimateDivEnabled(EVT VT,MachineFunction & MF) const getRecipEstimateDivEnabled() argument
2256 getSqrtRefinementSteps(EVT VT,MachineFunction & MF) const getSqrtRefinementSteps() argument
2261 getDivRefinementSteps(EVT VT,MachineFunction & MF) const getDivRefinementSteps() argument
[all...]
H A DCallingConvLower.cpp103 MVT VT = Outs[i].VT; in CheckReturn() local
117 MVT VT = Outs[i].VT; in AnalyzeReturn() local
165 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
178 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult()
193 static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) { in isValueTypeInRegForCC()
202 MVT VT, CCAssignFn Fn) { in getRemainingRegParmsForType()
H A DValueTypes.cpp39 EVT VT; in getExtendedIntegerVT() local
45 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, in getExtendedVectorVT() argument
54 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, ElementCount EC) { in getExtendedVectorVT() argument
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp744 MVT VT = Node->getSimpleValueType(0); Promote() local
785 MVT VT = Node->getOperand(IsStrict ? 1 : 0).getSimpleValueType(); PromoteINT_TO_FP() local
823 MVT VT = Node->getSimpleValueType(0); PromoteFP_TO_INT() local
1153 EVT VT = Node->getValueType(0); ExpandSELECT() local
1206 EVT VT = Node->getValueType(0); ExpandSEXTINREG() local
1228 EVT VT = Node->getValueType(0); ExpandANY_EXTEND_VECTOR_INREG() local
1263 EVT VT = Node->getValueType(0); ExpandSIGN_EXTEND_VECTOR_INREG() local
1287 EVT VT = Node->getValueType(0); ExpandZERO_EXTEND_VECTOR_INREG() local
1321 createBSWAPShuffleMask(EVT VT,SmallVectorImpl<int> & ShuffleMask) createBSWAPShuffleMask() argument
1329 EVT VT = Node->getValueType(0); ExpandBSWAP() local
1362 EVT VT = Node->getValueType(0); ExpandBITREVERSE() local
1427 EVT VT = Mask.getValueType(); ExpandVSELECT() local
1478 EVT VT = Mask.getValueType(); ExpandVP_SELECT() local
1542 EVT VT = Node->getValueType(0); ExpandVP_REM() local
1589 EVT VT = Src.getValueType(); ExpandUINT_TO_FLOAT() local
1691 EVT VT = Node->getValueType(0); ExpandFSUB() local
1767 EVT VT = Node->getValueType(0); ExpandSETCC() local
1847 EVT VT = Node->getValueType(0); UnrollStrictFPOp() local
1906 EVT VT = Node->getValueType(0); UnrollVSETCC() local
[all...]
H A DResourcePriorityQueue.cpp93 MVT VT = ScegN->getSimpleValueType(i); in numberRCValPredInSU() local
131 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU() local
326 MVT VT = SU->getNode()->getSimpleValueType(i); in rawRegPressureDelta() local
335 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta() local
474 MVT VT = ScegN->getSimpleValueType(i); in scheduledNode() local
485 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode() local
H A DSelectionDAG.cpp126 isValueValidForType(EVT VT,const APFloat & Val) isValueValidForType() argument
1118 EVT VT = N->getValueType(0); VerifySDNode() local
1194 EVT VT = cast<VTSDNode>(N)->getVT(); RemoveNodeFromCSEMaps() local
1429 getFPExtendOrRound(SDValue Op,const SDLoc & DL,EVT VT) getFPExtendOrRound() argument
1438 getStrictFPExtendOrRound(SDValue Op,SDValue Chain,const SDLoc & DL,EVT VT) getStrictFPExtendOrRound() argument
1450 getAnyExtOrTrunc(SDValue Op,const SDLoc & DL,EVT VT) getAnyExtOrTrunc() argument
1456 getSExtOrTrunc(SDValue Op,const SDLoc & DL,EVT VT) getSExtOrTrunc() argument
1462 getZExtOrTrunc(SDValue Op,const SDLoc & DL,EVT VT) getZExtOrTrunc() argument
1469 getBitcastedAnyExtOrTrunc(SDValue Op,const SDLoc & DL,EVT VT) getBitcastedAnyExtOrTrunc() argument
1484 getBitcastedSExtOrTrunc(SDValue Op,const SDLoc & DL,EVT VT) getBitcastedSExtOrTrunc() argument
1499 getBitcastedZExtOrTrunc(SDValue Op,const SDLoc & DL,EVT VT) getBitcastedZExtOrTrunc() argument
1513 getBoolExtOrTrunc(SDValue Op,const SDLoc & SL,EVT VT,EVT OpVT) getBoolExtOrTrunc() argument
1522 getZeroExtendInReg(SDValue Op,const SDLoc & DL,EVT VT) getZeroExtendInReg() argument
1540 getPtrExtOrTrunc(SDValue Op,const SDLoc & DL,EVT VT) getPtrExtOrTrunc() argument
1546 getPtrExtendInReg(SDValue Op,const SDLoc & DL,EVT VT) getPtrExtendInReg() argument
1552 getNegative(SDValue Val,const SDLoc & DL,EVT VT) getNegative() argument
1557 getNOT(const SDLoc & DL,SDValue Val,EVT VT) getNOT() argument
1561 getLogicalNOT(const SDLoc & DL,SDValue Val,EVT VT) getLogicalNOT() argument
1567 getVPLogicalNOT(const SDLoc & DL,SDValue Val,SDValue Mask,SDValue EVL,EVT VT) getVPLogicalNOT() argument
1572 getVPPtrExtOrTrunc(const SDLoc & DL,EVT VT,SDValue Op,SDValue Mask,SDValue EVL) getVPPtrExtOrTrunc() argument
1577 getVPZExtOrTrunc(const SDLoc & DL,EVT VT,SDValue Op,SDValue Mask,SDValue EVL) getVPZExtOrTrunc() argument
1586 getBoolConstant(bool V,const SDLoc & DL,EVT VT,EVT OpVT) getBoolConstant() argument
1601 getConstant(uint64_t Val,const SDLoc & DL,EVT VT,bool isT,bool isO) getConstant() argument
1610 getConstant(const APInt & Val,const SDLoc & DL,EVT VT,bool isT,bool isO) getConstant() argument
1616 getConstant(const ConstantInt & Val,const SDLoc & DL,EVT VT,bool isT,bool isO) getConstant() argument
1731 getShiftAmountConstant(uint64_t Val,EVT VT,const SDLoc & DL,bool LegalTypes) getShiftAmountConstant() argument
1743 getConstantFP(const APFloat & V,const SDLoc & DL,EVT VT,bool isTarget) getConstantFP() argument
1749 getConstantFP(const ConstantFP & V,const SDLoc & DL,EVT VT,bool isTarget) getConstantFP() argument
1780 getConstantFP(double Val,const SDLoc & DL,EVT VT,bool isTarget) getConstantFP() argument
1799 getGlobalAddress(const GlobalValue * GV,const SDLoc & DL,EVT VT,int64_t Offset,bool isTargetGA,unsigned TargetFlags) getGlobalAddress() argument
1831 getFrameIndex(int FI,EVT VT,bool isTarget) getFrameIndex() argument
1846 getJumpTable(int JTI,EVT VT,bool isTarget,unsigned TargetFlags) getJumpTable() argument
1872 getConstantPool(const Constant * C,EVT VT,MaybeAlign Alignment,int Offset,bool isTarget,unsigned TargetFlags) getConstantPool() argument
1901 getConstantPool(MachineConstantPoolValue * C,EVT VT,MaybeAlign Alignment,int Offset,bool isTarget,unsigned TargetFlags) getConstantPool() argument
1940 getValueType(EVT VT) getValueType() argument
1954 getExternalSymbol(const char * Sym,EVT VT) getExternalSymbol() argument
1962 getMCSymbol(MCSymbol * Sym,EVT VT) getMCSymbol() argument
1971 getTargetExternalSymbol(const char * Sym,EVT VT,unsigned TargetFlags) getTargetExternalSymbol() argument
1994 getVScale(const SDLoc & DL,EVT VT,APInt MulImm,bool ConstantFold) getVScale() argument
2013 getElementCount(const SDLoc & DL,EVT VT,ElementCount EC,bool ConstantFold) getElementCount() argument
2048 getVectorShuffle(EVT VT,const SDLoc & dl,SDValue N1,SDValue N2,ArrayRef<int> Mask) getVectorShuffle() argument
2219 EVT VT = SV.getValueType(0); getCommutedVectorShuffle() local
2228 getRegister(unsigned RegNo,EVT VT) getRegister() argument
2281 getBlockAddress(const BlockAddress * BA,EVT VT,int64_t Offset,bool isTarget,unsigned TargetFlags) getBlockAddress() argument
2331 getBitcast(EVT VT,SDValue V) getBitcast() argument
2338 getAddrSpaceCast(const SDLoc & dl,EVT VT,SDValue Ptr,unsigned SrcAS,unsigned DestAS) getAddrSpaceCast() argument
2377 EVT VT = Node->getValueType(0); expandVAArg() local
2421 getReducedAlign(EVT VT,bool UseABI) getReducedAlign() argument
2462 CreateStackTemporary(EVT VT,unsigned minAlign) CreateStackTemporary() argument
2486 FoldSetCC(EVT VT,SDValue N1,SDValue N2,ISD::CondCode Cond,const SDLoc & dl) FoldSetCC() argument
2680 EVT VT = Op.getValueType(); computeVectorKnownZeroElements() local
2705 EVT VT = V.getValueType(); isSplatValue() local
2889 EVT VT = V.getValueType(); isSplatValue() local
2905 EVT VT = V.getValueType(); getSplatSourceVector() local
3050 EVT VT = Op.getValueType(); computeKnownBits() local
3618 EVT VT = LD->getMemoryVT(); computeKnownBits() local
3622 EVT VT = LD->getValueType(0); computeKnownBits() local
3697 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); computeKnownBits() local
3977 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); computeKnownBits() local
4261 EVT VT = Op.getValueType(); ComputeNumSignBits() local
4274 EVT VT = Op.getValueType(); ComputeNumSignBits() local
4919 EVT VT = Op.getValueType(); isGuaranteedNotToBeUndefOrPoison() local
4994 EVT VT = Op.getValueType(); canCreateUndefOrPoison() local
5009 EVT VT = Op.getValueType(); canCreateUndefOrPoison() local
5427 FoldSTEP_VECTOR(const SDLoc & DL,EVT VT,SDValue Step,SelectionDAG & DAG) FoldSTEP_VECTOR() argument
5435 FoldBUILD_VECTOR(const SDLoc & DL,EVT VT,ArrayRef<SDValue> Ops,SelectionDAG & DAG) FoldBUILD_VECTOR() argument
5471 foldCONCAT_VECTORS(const SDLoc & DL,EVT VT,ArrayRef<SDValue> Ops,SelectionDAG & DAG) foldCONCAT_VECTORS() argument
5557 getNode(unsigned Opcode,const SDLoc & DL,EVT VT) getNode() argument
5574 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1) getNode() argument
5582 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,const SDNodeFlags Flags) getNode() argument
6006 FoldSymbolOffset(unsigned Opcode,EVT VT,const GlobalAddressSDNode * GA,const SDNode * N2) FoldSymbolOffset() argument
6052 FoldConstantArithmetic(unsigned Opcode,const SDLoc & DL,EVT VT,ArrayRef<SDValue> Ops) FoldConstantArithmetic() argument
6429 foldConstantFPMath(unsigned Opcode,const SDLoc & DL,EVT VT,ArrayRef<SDValue> Ops) foldConstantFPMath() argument
6535 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2) getNode() argument
6564 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,const SDNodeFlags Flags) getNode() argument
7058 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDValue N3) getNode() argument
7066 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDValue N3,const SDNodeFlags Flags) getNode() argument
7240 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDValue N3,SDValue N4) getNode() argument
7246 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDValue N3,SDValue N4,SDValue N5) getNode() argument
7276 getMemsetValue(SDValue Value,EVT VT,SelectionDAG & DAG,const SDLoc & dl) getMemsetValue() argument
7318 getMemsetStringVal(EVT VT,const SDLoc & dl,SelectionDAG & DAG,const TargetLowering & TLI,const ConstantDataArraySlice & Slice) getMemsetStringVal() argument
7363 EVT VT = Base.getValueType(); getMemBasePlusOffset() local
7520 EVT VT = MemOps[i]; getMemcpyLoadsAndStores() local
7710 EVT VT = MemOps[i]; getMemmoveLoadsAndStores() local
7731 EVT VT = MemOps[i]; getMemmoveLoadsAndStores() local
7832 EVT VT = MemOps[i]; getMemsetStores() local
8294 EVT VT = Val.getValueType(); getAtomic() local
8303 getAtomic(unsigned Opcode,const SDLoc & dl,EVT MemVT,EVT VT,SDValue Chain,SDValue Ptr,MachineMemOperand * MMO) getAtomic() argument
8477 getLoad(ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,const SDLoc & dl,SDValue Chain,SDValue Ptr,SDValue Offset,MachinePointerInfo PtrInfo,EVT MemVT,Align Alignment,MachineMemOperand::Flags MMOFlags,const AAMDNodes & AAInfo,const MDNode * Ranges) getLoad() argument
8501 getLoad(ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,const SDLoc & dl,SDValue Chain,SDValue Ptr,SDValue Offset,EVT MemVT,MachineMemOperand * MMO) getLoad() argument
8550 getLoad(EVT VT,const SDLoc & dl,SDValue Chain,SDValue Ptr,MachinePointerInfo PtrInfo,MaybeAlign Alignment,MachineMemOperand::Flags MMOFlags,const AAMDNodes & AAInfo,const MDNode * Ranges) getLoad() argument
8560 getLoad(EVT VT,const SDLoc & dl,SDValue Chain,SDValue Ptr,MachineMemOperand * MMO) getLoad() argument
8568 getExtLoad(ISD::LoadExtType ExtType,const SDLoc & dl,EVT VT,SDValue Chain,SDValue Ptr,MachinePointerInfo PtrInfo,EVT MemVT,MaybeAlign Alignment,MachineMemOperand::Flags MMOFlags,const AAMDNodes & AAInfo) getExtLoad() argument
8579 getExtLoad(ISD::LoadExtType ExtType,const SDLoc & dl,EVT VT,SDValue Chain,SDValue Ptr,EVT MemVT,MachineMemOperand * MMO) getExtLoad() argument
8625 EVT VT = Val.getValueType(); getStore() local
8676 EVT VT = Val.getValueType(); getTruncStore() local
8749 getLoadVP(ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,const SDLoc & dl,SDValue Chain,SDValue Ptr,SDValue Offset,SDValue Mask,SDValue EVL,MachinePointerInfo PtrInfo,EVT MemVT,Align Alignment,MachineMemOperand::Flags MMOFlags,const AAMDNodes & AAInfo,const MDNode * Ranges,bool IsExpanding) getLoadVP() argument
8772 getLoadVP(ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,const SDLoc & dl,SDValue Chain,SDValue Ptr,SDValue Offset,SDValue Mask,SDValue EVL,EVT MemVT,MachineMemOperand * MMO,bool IsExpanding) getLoadVP() argument
8806 getLoadVP(EVT VT,const SDLoc & dl,SDValue Chain,SDValue Ptr,SDValue Mask,SDValue EVL,MachinePointerInfo PtrInfo,MaybeAlign Alignment,MachineMemOperand::Flags MMOFlags,const AAMDNodes & AAInfo,const MDNode * Ranges,bool IsExpanding) getLoadVP() argument
8819 getLoadVP(EVT VT,const SDLoc & dl,SDValue Chain,SDValue Ptr,SDValue Mask,SDValue EVL,MachineMemOperand * MMO,bool IsExpanding) getLoadVP() argument
8828 getExtLoadVP(ISD::LoadExtType ExtType,const SDLoc & dl,EVT VT,SDValue Chain,SDValue Ptr,SDValue Mask,SDValue EVL,MachinePointerInfo PtrInfo,EVT MemVT,MaybeAlign Alignment,MachineMemOperand::Flags MMOFlags,const AAMDNodes & AAInfo,bool IsExpanding) getExtLoadVP() argument
8841 getExtLoadVP(ISD::LoadExtType ExtType,const SDLoc & dl,EVT VT,SDValue Chain,SDValue Ptr,SDValue Mask,SDValue EVL,EVT MemVT,MachineMemOperand * MMO,bool IsExpanding) getExtLoadVP() argument
8927 EVT VT = Val.getValueType(); getTruncStoreVP() local
9002 getStridedLoadVP(ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,const SDLoc & DL,SDValue Chain,SDValue Ptr,SDValue Offset,SDValue Stride,SDValue Mask,SDValue EVL,MachinePointerInfo PtrInfo,EVT MemVT,Align Alignment,MachineMemOperand::Flags MMOFlags,const AAMDNodes & AAInfo,const MDNode * Ranges,bool IsExpanding) getStridedLoadVP() argument
9025 getStridedLoadVP(ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,const SDLoc & DL,SDValue Chain,SDValue Ptr,SDValue Offset,SDValue Stride,SDValue Mask,SDValue EVL,EVT MemVT,MachineMemOperand * MMO,bool IsExpanding) getStridedLoadVP() argument
9059 getStridedLoadVP(EVT VT,const SDLoc & DL,SDValue Chain,SDValue Ptr,SDValue Stride,SDValue Mask,SDValue EVL,MachinePointerInfo PtrInfo,MaybeAlign Alignment,MachineMemOperand::Flags MMOFlags,const AAMDNodes & AAInfo,const MDNode * Ranges,bool IsExpanding) getStridedLoadVP() argument
9069 getStridedLoadVP(EVT VT,const SDLoc & DL,SDValue Chain,SDValue Ptr,SDValue Stride,SDValue Mask,SDValue EVL,MachineMemOperand * MMO,bool IsExpanding) getStridedLoadVP() argument
9080 getExtStridedLoadVP(ISD::LoadExtType ExtType,const SDLoc & DL,EVT VT,SDValue Chain,SDValue Ptr,SDValue Stride,SDValue Mask,SDValue EVL,MachinePointerInfo PtrInfo,EVT MemVT,MaybeAlign Alignment,MachineMemOperand::Flags MMOFlags,const AAMDNodes & AAInfo,bool IsExpanding) getExtStridedLoadVP() argument
9092 getExtStridedLoadVP(ISD::LoadExtType ExtType,const SDLoc & DL,EVT VT,SDValue Chain,SDValue Ptr,SDValue Stride,SDValue Mask,SDValue EVL,EVT MemVT,MachineMemOperand * MMO,bool IsExpanding) getExtStridedLoadVP() argument
9179 EVT VT = Val.getValueType(); getTruncStridedStoreVP() local
9254 getGatherVP(SDVTList VTs,EVT VT,const SDLoc & dl,ArrayRef<SDValue> Ops,MachineMemOperand * MMO,ISD::MemIndexType IndexType) getGatherVP() argument
9297 getScatterVP(SDVTList VTs,EVT VT,const SDLoc & dl,ArrayRef<SDValue> Ops,MachineMemOperand * MMO,ISD::MemIndexType IndexType) getScatterVP() argument
9341 getMaskedLoad(EVT VT,const SDLoc & dl,SDValue Chain,SDValue Base,SDValue Offset,SDValue Mask,SDValue PassThru,EVT MemVT,MachineMemOperand * MMO,ISD::MemIndexedMode AM,ISD::LoadExtType ExtTy,bool isExpanding) getMaskedLoad() argument
9682 getVAArg(EVT VT,const SDLoc & dl,SDValue Chain,SDValue Ptr,SDValue SV,unsigned Align) getVAArg() argument
9688 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,ArrayRef<SDUse> Ops) getNode() argument
9704 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,ArrayRef<SDValue> Ops) getNode() argument
9712 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,ArrayRef<SDValue> Ops,const SDNodeFlags Flags) getNode() argument
10053 getVTList(EVT VT) getVTList() argument
10284 SelectNodeTo(SDNode * N,unsigned MachineOpc,EVT VT) SelectNodeTo() argument
10290 SelectNodeTo(SDNode * N,unsigned MachineOpc,EVT VT,SDValue Op1) SelectNodeTo() argument
10297 SelectNodeTo(SDNode * N,unsigned MachineOpc,EVT VT,SDValue Op1,SDValue Op2) SelectNodeTo() argument
10305 SelectNodeTo(SDNode * N,unsigned MachineOpc,EVT VT,SDValue Op1,SDValue Op2,SDValue Op3) SelectNodeTo() argument
10313 SelectNodeTo(SDNode * N,unsigned MachineOpc,EVT VT,ArrayRef<SDValue> Ops) SelectNodeTo() argument
10492 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT) getMachineNode() argument
10498 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT,SDValue Op1) getMachineNode() argument
10505 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT,SDValue Op1,SDValue Op2) getMachineNode() argument
10512 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT,SDValue Op1,SDValue Op2,SDValue Op3) getMachineNode() argument
10520 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT,ArrayRef<SDValue> Ops) getMachineNode() argument
10609 getTargetExtractSubreg(int SRIdx,const SDLoc & DL,EVT VT,SDValue Operand) getTargetExtractSubreg() argument
10619 getTargetInsertSubreg(int SRIdx,const SDLoc & DL,EVT VT,SDValue Operand,SDValue Subreg) getTargetInsertSubreg() argument
11591 EVT VT = V.getValueType(); isNeutralConstant() local
11644 EVT VT = N.getValueType(); isConstOrConstSplat() local
11689 EVT VT = N.getValueType(); isConstOrConstSplatFP() local
11744 GlobalAddressSDNode(unsigned Opc,unsigned Order,const DebugLoc & DL,const GlobalValue * GA,EVT VT,int64_t o,unsigned TF) GlobalAddressSDNode() argument
11751 AddrSpaceCastSDNode(unsigned Order,const DebugLoc & dl,EVT VT,unsigned SrcAS,unsigned DestAS) AddrSpaceCastSDNode() argument
11794 getValueTypeList(EVT VT) getValueTypeList() argument
12051 EVT VT = N->getValueType(0); UnrollVectorOp() local
12210 EVT VT = LD->getMemoryVT(); areNonVolatileConsecutiveLoads() local
12291 GetDependentSplitDestVTs(const EVT & VT,const EVT & EnvVT,bool * HiIsEmpty) const GetDependentSplitDestVTs() argument
12346 EVT VT = N.getValueType(); SplitEVL() local
12361 EVT VT = N.getValueType(); WidenVector() local
12372 EVT VT = Op.getValueType(); ExtractVectorElements() local
12400 EVT VT = getValueType(0); isConstantSplat() local
12733 isSplatMask(const int * Mask,EVT VT) isSplatMask() argument
12824 getNeutralElement(unsigned Opcode,const SDLoc & DL,EVT VT,SDNodeFlags Flags) getNeutralElement() argument
[all...]
H A DDAGCombiner.cpp258 TLI.isTypeLegal(EVT(VT)) && in DAGCombiner() local
835 hasOperation(unsigned Opcode,EVT VT) hasOperation() argument
854 isTypeLegal(const EVT & VT) isTypeLegal() argument
912 isOperationLegalOrCustom(unsigned Op,EVT VT,bool LegalOnly=false) const isOperationLegalOrCustom() argument
967 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue Operand) getNode() argument
975 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2) getNode() argument
984 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDValue N3) getNode() argument
993 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue Operand,SDNodeFlags Flags) getNode() argument
1002 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDNodeFlags Flags) getNode() argument
1011 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDValue N3,SDNodeFlags Flags) getNode() argument
1020 isOperationLegalOrCustom(unsigned Op,EVT VT,bool LegalOnly=false) const isOperationLegalOrCustom() argument
1243 EVT VT = LoadStore->getMemoryVT(); reassociationCanBreakAddressingModePattern() local
1270 EVT VT = LoadStore->getMemoryVT(); reassociationCanBreakAddressingModePattern() local
1287 EVT VT = N0.getValueType(); reassociateOpsCommutative() local
1403 reassociateReduction(unsigned RedOpc,unsigned Opc,const SDLoc & DL,EVT VT,SDValue N0,SDValue N1,SDNodeFlags Flags) reassociateReduction() argument
1504 EVT VT = Load->getValueType(0); ReplaceLoadWithPromotedLoad() local
1592 EVT VT = Op.getValueType(); PromoteIntBinOp() local
1660 EVT VT = Op.getValueType(); PromoteIntShiftOp() local
1709 EVT VT = Op.getValueType(); PromoteExtend() local
1740 EVT VT = Op.getValueType(); PromoteLoad() local
2421 EVT VT; canFoldInAddressingMode() local
2498 EVT VT = N->getValueType(0); foldSelectWithIdentityConstant() local
2527 EVT VT = BO->getValueType(0); foldBinOpIntoSelect() local
2655 EVT VT = C.getValueType(); foldAddSubBoolOfMaskedVal() local
2684 EVT VT = ShiftOp.getValueType(); foldAddSubOfSignBit() local
2717 EVT VT = N0.getValueType(); visitADDLike() local
2965 EVT VT = N0.getValueType(); visitADD() local
3026 EVT VT = N0.getValueType(); visitADDSAT() local
3098 EVT VT = V->getValueType(0); getAsCarry() local
3124 EVT VT = N0.getValueType(); foldAddSubMasked1() local
3143 EVT VT = N0.getValueType(); visitADDLikeCommutative() local
3235 EVT VT = N0.getValueType(); visitADDC() local
3282 EVT VT = V.getValueType(); extractBooleanFlip() local
3307 EVT VT = N0.getValueType(); visitADDO() local
3357 EVT VT = N0.getValueType(); visitUADDOLike() local
3420 EVT VT = N0.getValueType(); visitUADDO_CARRY() local
3491 EVT VT = Combiner.getSetCCResultType(Carry0.getValueType()); combineUADDO_CARRYDiamond() local
3792 tryFoldToZero(const SDLoc & DL,const TargetLowering & TLI,EVT VT,SelectionDAG & DAG,bool LegalOperations) tryFoldToZero() argument
3804 EVT VT = N0.getValueType(); visitSUB() local
4185 EVT VT = N0.getValueType(); visitSUBSAT() local
4225 EVT VT = N0.getValueType(); visitSUBC() local
4253 EVT VT = N0.getValueType(); visitSUBO() local
4342 EVT VT = N0.getValueType(); visitMULFIX() local
4363 EVT VT = N0.getValueType(); visitMUL() local
4631 EVT VT = Node->getValueType(0); useDivRem() local
4693 EVT VT = N->getValueType(0); simplifyDivRem() local
4739 EVT VT = N->getValueType(0); visitSDIV() local
4817 EVT VT = N->getValueType(0); visitSDIVLike() local
4887 EVT VT = N->getValueType(0); visitUDIV() local
4941 EVT VT = N->getValueType(0); visitUDIVLike() local
4997 EVT VT = N->getValueType(0); visitREM() local
5090 EVT VT = N->getValueType(0); visitMULHS() local
5150 EVT VT = N->getValueType(0); visitMULHU() local
5228 EVT VT = N->getValueType(0); visitAVG() local
5272 EVT VT = N->getValueType(0); visitABD() local
5365 EVT VT = N->getValueType(0); visitSMUL_LOHI() local
5407 EVT VT = N->getValueType(0); visitUMUL_LOHI() local
5458 EVT VT = N0.getValueType(); visitMULO() local
5681 EVT VT = N0.getValueType(); visitIMINMAX() local
5758 EVT VT = N0.getValueType(); hoistLogicOpWithSameOpcodeHands() local
5953 EVT VT = N0.getValueType(); foldLogicOfSetCCs() local
6174 EVT VT = LogicOp->getValueType(0); foldAndOrOfSETCC() local
6363 EVT VT = N1.getValueType(); visitANDLike() local
6584 EVT VT = Op.getOpcode() == ISD::AssertZext ? SearchForAndLoads() local
6612 MVT VT = SDValue(NodeToMask, i).getSimpleValueType(); SearchForAndLoads() local
6744 EVT VT = N->getValueType(0); unfoldExtremeBitClearingToShifts() local
6834 EVT VT = N1.getValueType(); foldAndToUsubsat() local
6901 EVT VT = N->getValueType(0); foldLogicOfShifts() local
6940 EVT VT = N->getValueType(0); foldLogicTreeOfShifts() local
6948 EVT VT = N1.getValueType(); visitAND() local
7370 EVT VT = N->getValueType(0); MatchBSwapHWordLow() local
7594 matchBSwapHWordOrAndAnd(const TargetLowering & TLI,SelectionDAG & DAG,SDNode * N,SDValue N0,SDValue N1,EVT VT,EVT ShiftAmountTy) matchBSwapHWordOrAndAnd() argument
7640 EVT VT = N->getValueType(0); MatchBSwapHWord() local
7702 EVT VT = N1.getValueType(); visitORLike() local
7755 EVT VT = N0.getValueType(); visitORCommutative() local
7836 EVT VT = N1.getValueType(); visitOR() local
8311 EVT VT = Shifted.getValueType(); MatchRotatePosNeg() local
8332 EVT VT = N0.getValueType(); MatchFunnelPosNeg() local
8395 EVT VT = LHS.getValueType(); MatchRotate() local
9096 EVT VT = N->getValueType(0); MatchLoadCombine() local
9298 EVT VT = N->getValueType(0); unfoldMaskedMerge() local
9377 EVT VT = N0.getValueType(); visitXOR() local
9665 EVT VT = Shift->getValueType(0); combineShiftOfShiftedLogic() local
9731 EVT VT = N->getValueType(0); visitShiftByConstant() local
9769 EVT VT = N->getValueType(0); visitRotate() local
9851 EVT VT = N0.getValueType(); visitSHL() local
10267 EVT VT = N->getValueType(0); foldBitOrderCrossLogicOp() local
10301 EVT VT = N0.getValueType(); visitSRA() local
10505 EVT VT = N0.getValueType(); visitSRL() local
10764 EVT VT = N->getValueType(0); visitFunnelShift() local
10883 EVT VT = N0.getValueType(); visitSHLSAT() local
10921 EVT VT = N->getValueType(0); foldABSToABD() local
10982 EVT VT = N->getValueType(0); visitABS() local
11017 EVT VT = N->getValueType(0); visitBSWAP() local
11080 EVT VT = N->getValueType(0); visitBITREVERSE() local
11094 EVT VT = N->getValueType(0); visitCTLZ() local
11111 EVT VT = N->getValueType(0); visitCTLZ_ZERO_UNDEF() local
11123 EVT VT = N->getValueType(0); visitCTTZ() local
11140 EVT VT = N->getValueType(0); visitCTTZ_ZERO_UNDEF() local
11152 EVT VT = N->getValueType(0); visitCTPOP() local
11167 EVT VT = LHS.getValueType(); isLegalToCombineMinNumMaxNum() local
11174 combineMinNumMaxNumImpl(const SDLoc & DL,EVT VT,SDValue LHS,SDValue RHS,SDValue True,SDValue False,ISD::CondCode CC,const TargetLowering & TLI,SelectionDAG & DAG) combineMinNumMaxNumImpl() argument
11220 combineMinNumMaxNum(const SDLoc & DL,EVT VT,SDValue LHS,SDValue RHS,SDValue True,SDValue False,ISD::CondCode CC) combineMinNumMaxNum() argument
11269 EVT VT = N->getValueType(0); foldSelectOfConstantsUsingSra() local
11297 shouldConvertSelectOfConstantsToMath(const SDValue & Cond,EVT VT,const TargetLowering & TLI) shouldConvertSelectOfConstantsToMath() argument
11320 EVT VT = N->getValueType(0); foldSelectOfConstants() local
11440 EVT VT = N->getValueType(0); foldBoolSelectToLogic() local
11473 EVT VT = N->getValueType(0); foldVSelectToSignBitSplatMask() local
11531 EVT VT = N->getValueType(0); visitSELECT() local
11710 EVT VT = N->getValueType(0); ConvertSelectToConcatVector() local
11768 EVT VT = BasePtr.getValueType(); refineUniformBase() local
12094 EVT VT = N->getValueType(0); foldVSelectOfConstants() local
12157 EVT VT = N->getValueType(0); visitVSELECT() local
12499 EVT VT = N->getValueType(0); visitSETCC() local
12680 EVT VT = N->getValueType(0); tryToFoldExtendSelectLoad() local
12727 EVT VT = N->getValueType(0); tryToFoldExtendOfConstant() local
12806 ExtendUsesToFormExtLoad(EVT VT,SDNode * N,SDValue N0,unsigned ExtOpc,SmallVectorImpl<SDNode * > & ExtendNodes,const TargetLowering & TLI) ExtendUsesToFormExtLoad() argument
12989 EVT VT = N->getValueType(0); CombineZExtLogicopShiftLoad() local
13075 EVT VT = Cast->getValueType(0); matchVSelectOpSizesWithSetCC() local
13109 tryToFoldExtOfExtload(SelectionDAG & DAG,DAGCombiner & Combiner,const TargetLowering & TLI,EVT VT,bool LegalOperations,SDNode * N,SDValue N0,ISD::LoadExtType ExtLoadType) tryToFoldExtOfExtload() argument
13140 tryToFoldExtOfLoad(SelectionDAG & DAG,DAGCombiner & Combiner,const TargetLowering & TLI,EVT VT,bool LegalOperations,SDNode * N,SDValue N0,ISD::LoadExtType ExtLoadType,ISD::NodeType ExtOpc) tryToFoldExtOfLoad() argument
13183 tryToFoldExtOfMaskedLoad(SelectionDAG & DAG,const TargetLowering & TLI,EVT VT,bool LegalOperations,SDNode * N,SDValue N0,ISD::LoadExtType ExtLoadType,ISD::NodeType ExtOpc) tryToFoldExtOfMaskedLoad() argument
13223 EVT VT = N->getValueType(0); foldExtendedSignBitTest() local
13254 EVT VT = N->getValueType(0); foldSextSetcc() local
13373 EVT VT = N->getValueType(0); visitSIGN_EXTEND() local
13601 EVT VT = Extend->getValueType(0); widenCtPop() local
13618 EVT VT = Extend->getValueType(0); widenAbs() local
13642 EVT VT = N->getValueType(0); visitZERO_EXTEND() local
13920 EVT VT = N->getValueType(0); visitANY_EXTEND() local
14180 EVT VT = N->getValueType(0); reduceLoadWidth() local
14414 EVT VT = N->getValueType(0); visitSIGN_EXTEND_INREG() local
14616 EVT VT = N->getValueType(0); foldExtendVectorInregToExtendOfSubvector() local
14643 EVT VT = N->getValueType(0); visitEXTEND_VECTOR_INREG() local
14668 EVT VT = N->getValueType(0); visitTRUNCATE() local
15018 CombineConsecutiveLoads(SDNode * N,EVT VT) CombineConsecutiveLoads() argument
15058 EVT VT = N->getValueType(0); foldBitcastedFPLogic() local
15095 __anon29909ce23002(SDValue Op, EVT VT) foldBitcastedFPLogic() argument
15123 EVT VT = N->getValueType(0); visitBITCAST() local
15384 EVT VT = N->getValueType(0); visitBUILD_PAIR() local
15492 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, ConstantFoldBITCASTofBUILD_VECTOR() local
15541 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); ConstantFoldBITCASTofBUILD_VECTOR() local
15564 EVT VT = N->getValueType(0); visitFADDForFMACombine() local
15801 EVT VT = N->getValueType(0); visitFSUBForFMACombine() local
16130 EVT VT = N->getValueType(0); visitFMULForFMADistributiveCombine() local
16236 EVT VT = N->getValueType(0); visitFADD() local
16428 EVT VT = N->getValueType(0); visitSTRICT_FADD() local
16456 EVT VT = N->getValueType(0); visitFSUB() local
16551 EVT VT = N->getValueType(0); combineFMulOrFDivWithIntPow2() local
16645 EVT VT = N->getValueType(0); visitFMUL() local
16795 EVT VT = N->getValueType(0); visitFMA() local
16920 EVT VT = N->getValueType(0); visitFMAD() local
16960 EVT VT = N->getValueType(0); combineRepeatedFPDivisors() local
17014 EVT VT = N->getValueType(0); visitFDIV() local
17161 EVT VT = N->getValueType(0); visitFREM() local
17231 EVT VT = N->getValueType(0); visitFCOPYSIGN() local
17285 EVT VT = N->getValueType(0); visitFPOW() local
17360 EVT VT = N->getValueType(0); foldFPToIntToFP() local
17381 EVT VT = N->getValueType(0); visitSINT_TO_FP() local
17433 EVT VT = N->getValueType(0); visitUINT_TO_FP() local
17473 EVT VT = N->getValueType(0); FoldIntToFPToInt() local
17514 EVT VT = N->getValueType(0); visitFP_TO_SINT() local
17529 EVT VT = N->getValueType(0); visitFP_TO_UINT() local
17544 EVT VT = N->getValueType(0); visitXRINT() local
17560 EVT VT = N->getValueType(0); visitFP_ROUND() local
17626 EVT VT = N->getValueType(0); visitFP_EXTEND() local
17683 EVT VT = N->getValueType(0); visitFCEIL() local
17694 EVT VT = N->getValueType(0); visitFTRUNC() local
17728 EVT VT = N->getValueType(0); visitFFLOOR() local
17739 EVT VT = N->getValueType(0); visitFNEG() local
17770 EVT VT = N->getValueType(0); visitFMinMax() local
17827 EVT VT = N->getValueType(0); visitFABS() local
18068 EVT VT = LD->getMemoryVT(); getCombineLoadStoreParts() local
18075 EVT VT = ST->getMemoryVT(); getCombineLoadStoreParts() local
18083 EVT VT = LD->getMemoryVT(); getCombineLoadStoreParts() local
18092 EVT VT = ST->getMemoryVT(); getCombineLoadStoreParts() local
19481 MVT VT = MVT::getIntegerVT(NumBytes * 8); ShrinkLoadReplaceStoreWithStore() local
19551 EVT VT = Value.getValueType(); ReduceLoadOpStoreWidth() local
19681 EVT VT = LD->getMemoryVT(); TransformFPLoadStorePair() local
21434 EVT VT = EVT::getIntegerVT(*DAG.getContext(), HalfValBitSize); splitMergedValStore() local
21566 EVT VT = DestVec.getValueType(); combineInsertEltToShuffle() local
21614 EVT VT = N->getValueType(0); combineInsertEltToLoad() local
21709 EVT VT = InVec.getValueType(); visitINSERT_VECTOR_ELT() local
22015 EVT VT = ExtElt->getValueType(0); scalarizeExtractedBinop() local
22533 EVT VT = N->getValueType(0); reduceBuildVecExtToExtBuildVec() local
22646 EVT VT = N->getValueType(0); reduceBuildVecTruncToBitCast() local
22729 EVT VT = N->getValueType(0); createBuildVecShuffle() local
22891 EVT VT = BV->getValueType(0); reduceBuildVecToShuffleWithZero() local
22955 EVT VT = N->getValueType(0); reduceBuildVecToShuffle() local
23217 EVT VT = N->getValueType(0); convertBuildVecZextToZext() local
23278 EVT VT = N->getValueType(0); convertBuildVecZextToBuildVecWithZeros() local
23384 EVT VT = N->getValueType(0); visitBUILD_VECTOR() local
23480 EVT VT = N->getValueType(0); combineConcatVectorOfScalars() local
23537 EVT VT = N->getValueType(0); combineConcatVectorOfConcatVectors() local
23575 EVT VT = N->getValueType(0); combineConcatVectorOfExtracts() local
23683 EVT VT = N->getValueType(0); combineConcatVectorOfCasts() local
23717 EVT VT = N->getValueType(0); combineConcatVectorOfShuffleAndItsOperands() local
23820 EVT VT = N->getValueType(0); visitCONCAT_VECTORS() local
24097 EVT VT = Extract->getValueType(0); narrowExtractedVectorBinOp() local
24201 EVT VT = Extract->getValueType(0); narrowExtractedVectorLoad() local
24611 EVT VT = Shuf->getValueType(0); foldShuffleOfConcatUndefs() local
24649 EVT VT = N->getValueType(0); partitionShuffleOfConcats() local
24730 EVT VT = SVN->getValueType(0); combineShuffleOfScalars() local
24811 canCombineShuffleToExtendVectorInreg(unsigned Opcode,EVT VT,std::function<bool (unsigned)> Match,SelectionDAG & DAG,const TargetLowering & TLI,bool LegalTypes,bool LegalOperations) canCombineShuffleToExtendVectorInreg() argument
24852 EVT VT = SVN->getValueType(0); combineShuffleToAnyExtendVectorInreg() local
24891 EVT VT = SVN->getValueType(0); combineShuffleToZeroExtendVectorInReg() local
25014 EVT VT = SVN->getValueType(0); combineTruncationShuffle() local
25073 EVT VT = Shuf->getValueType(0); combineShuffleOfSplatVal() local
25179 EVT VT = SVN->getValueType(0); combineShuffleOfBitcast() local
25260 EVT VT = OuterShuf->getValueType(0); formSplatFromShuffles() local
25375 EVT VT = N->getValueType(0); visitVECTOR_SHUFFLE() local
26029 EVT VT = N->getValueType(0); visitSCALAR_TO_VECTOR() local
26122 EVT VT = N->getValueType(0); visitINSERT_SUBVECTOR() local
26327 EVT VT = N0.getValueType(); visitVECREDUCE() local
26537 EVT VT = N->getValueType(0); XformToShuffleWithZero() local
26626 EVT VT = N->getValueType(0); scalarizeBinOpOfSplats() local
26670 EVT VT = N->getValueType(0); SimplifyVCastOp() local
26703 EVT VT = N->getValueType(0); SimplifyVBinOp() local
27171 EVT VT = N->getValueType(0); foldSignChangeInBitcast() local
27222 EVT VT = N2.getValueType(); convertSelectOfFPConstantsToLoadOffset() local
27275 EVT VT = N2.getValueType(); SimplifySelectCC() local
27432 SimplifySetCC(EVT VT,SDValue N0,SDValue N1,ISD::CondCode Cond,const SDLoc & DL,bool foldBooleans) SimplifySetCC() argument
27532 takeInexpensiveLog2(SelectionDAG & DAG,const SDLoc & DL,EVT VT,SDValue Op,unsigned Depth,bool AssumeNonZero) takeInexpensiveLog2() argument
27639 EVT VT = OutVT ? *OutVT : V.getValueType(); BuildLogBase2() local
27665 EVT VT = Op.getValueType(); BuildDivEstimate() local
27730 EVT VT = Arg.getValueType(); buildSqrtNROneConst() local
27762 EVT VT = Arg.getValueType(); buildSqrtNRTwoConst() local
27805 EVT VT = Op.getValueType(); buildSqrtEstimateImpl() local
[all...]
H A DLegalizeTypes.h61 getTypeAction(EVT VT) getTypeAction() argument
66 isTypeLegal(EVT VT) isTypeLegal() argument
71 isSimpleLegalType(EVT VT) isSimpleLegalType() argument
75 getSetCCResultType(EVT VT) getSetCCResultType() argument
[all...]
H A DLegalizeDAG.cpp266 ShuffleWithNarrowerEltType(EVT NVT,EVT VT,const SDLoc & dl,SDValue N1,SDValue N2,ArrayRef<int> Mask) const ShuffleWithNarrowerEltType() argument
305 EVT VT = CFP->getValueType(0); ExpandConstantFP() local
355 EVT VT = CP->getValueType(0); ExpandConstant() local
383 EVT VT = Tmp1.getValueType(); PerformInsertVectorEltInMemory() local
515 MVT VT = Value.getSimpleValueType(); LegalizeStoreOps() local
686 MVT VT = Node->getSimpleValueType(0); LegalizeLoadOps() local
1505 EVT VT = Node->getValueType(0); ExpandVectorBuildThroughStack() local
1722 EVT VT = Node->getValueType(0); ExpandDYNAMIC_STACKALLOC() local
1831 EVT VT = Node->getValueType(0); ExpandBVWithShuffles() local
1926 EVT VT = Node->getValueType(0); ExpandBUILD_VECTOR() local
2036 EVT VT = Node->getValueType(0); ExpandSPLAT_VECTOR() local
2115 EVT VT = Node->getValueType(0); ExpandFrexpLibCall() local
2387 EVT VT = Node->getValueType(0); expandLdexp() local
2500 EVT VT = Val.getValueType(); expandFrexp() local
2973 EVT VT = Op.getValueType(); ExpandPARITY() local
3149 EVT VT = Node->getValueType(0); ExpandNode() local
3172 EVT VT = Node->getValueType(0); ExpandNode() local
3203 EVT VT = Node->getValueType(0); ExpandNode() local
3296 EVT VT = Node->getValueType(0); ExpandNode() local
3409 EVT VT = Node->getValueType(0); ExpandNode() local
3571 EVT VT = Node->getValueType(0); ExpandNode() local
3587 EVT VT = Node->getValueType(0); ExpandNode() local
3676 EVT VT = Node->getValueType(0); ExpandNode() local
3687 EVT VT = Node->getValueType(0); ExpandNode() local
3705 EVT VT = Node->getValueType(0); ExpandNode() local
3718 EVT VT = Node->getValueType(0); ExpandNode() local
3730 MVT VT = LHS.getSimpleValueType(); ExpandNode() local
3760 EVT VT = Node->getValueType(0); ExpandNode() local
3861 EVT VT = LHS.getValueType(); ExpandNode() local
4078 EVT VT = Node->getValueType(0); ExpandNode() local
4093 EVT VT = Node->getValueType(0); ExpandNode() local
4203 EVT VT = Node->getValueType(0); ExpandNode() local
4277 EVT VT = Node->getValueType(0); ExpandNode() local
4357 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); ConvertNodeToLibcall() local
4753 EVT VT = Node->getValueType(0); ConvertNodeToLibcall() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp162 getPackedSVEVectorVT(EVT VT) getPackedSVEVectorVT() argument
202 getPromotedVTForPredicate(EVT VT) getPromotedVTForPredicate() argument
224 isPackedVectorType(EVT VT,SelectionDAG & DAG) isPackedVectorType() argument
415 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) AArch64TargetLowering() local
419 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) AArch64TargetLowering() local
583 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { AArch64TargetLowering() local
635 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { AArch64TargetLowering() local
933 for (MVT VT : MVT::fp_valuetypes()) { AArch64TargetLowering() local
939 for (MVT VT : MVT::integer_valuetypes()) AArch64TargetLowering() local
1215 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { AArch64TargetLowering() local
1416 for (MVT VT : MVT::scalable_vector_valuetypes()) { AArch64TargetLowering() local
1576 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) AArch64TargetLowering() local
1579 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) AArch64TargetLowering() local
1672 addTypeForNEON(MVT VT) addTypeForNEON() argument
1812 addTypeForFixedLengthSVE(MVT VT,bool StreamingSVE) addTypeForFixedLengthSVE() argument
1947 addDRTypeForNEON(MVT VT) addDRTypeForNEON() argument
1952 addQRTypeForNEON(MVT VT) addQRTypeForNEON() argument
2059 EVT VT = Op.getValueType(); optimizeLogicalImm() local
2090 EVT VT = Op.getValueType(); targetShrinkDemandedConstant() local
2203 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); computeKnownBitsForTargetNode() local
2218 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); computeKnownBitsForTargetNode() local
2234 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); computeKnownBitsForTargetNode() local
2255 EVT VT = Op.getValueType(); ComputeNumSignBitsForTargetNode() local
2290 allowsMisalignedMemoryAccesses(EVT VT,unsigned AddrSpace,Align Alignment,MachineMemOperand::Flags Flags,unsigned * Fast) const allowsMisalignedMemoryAccesses() argument
3150 EVT VT = LHS.getValueType(); emitStrictFPComparison() local
3170 EVT VT = LHS.getValueType(); emitComparison() local
3534 EVT VT = Op.getValueType(); getCmpOperandFoldingProfit() local
3546 EVT VT = RHS.getValueType(); getAArch64Cmp() local
3851 EVT VT = Value.getValueType(); valueToCarryFlag() local
3861 carryFlagToValue(SDValue Glue,EVT VT,SelectionDAG & DAG,bool Invert) carryFlagToValue() argument
3873 overflowFlagToValue(SDValue Glue,EVT VT,SelectionDAG & DAG) overflowFlagToValue() argument
3970 EVT VT = Op.getValueType(); LowerFP_EXTEND() local
4012 EVT VT = Op.getValueType(); LowerVectorFP_TO_INT() local
4255 EVT VT = Op.getValueType(); LowerVectorINT_TO_FP() local
4479 EVT VT = OpNode->getOperand(0).getValueType(); getConstantLaneNumOfExtractHalfOperand() local
4489 EVT VT = N.getValueType(); isExtendedBUILD_VECTOR() local
4514 EVT VT = N.getValueType(); skipExtensionForVectorMULL() local
4679 EVT VT = N0.getValueType(); selectUmullSmull() local
4708 EVT VT = Op.getValueType(); LowerMUL() local
4786 getPTrue(SelectionDAG & DAG,SDLoc DL,EVT VT,int Pattern) getPTrue() argument
4835 getSVEPredicateBitCast(EVT VT,SDValue Op,SelectionDAG & DAG) getSVEPredicateBitCast() argument
5502 shouldExtendGSIndex(EVT VT,EVT & EltTy) const shouldExtendGSIndex() argument
5613 EVT VT = Op.getValueType(); LowerMGATHER() local
5712 EVT VT = StoreVal.getValueType(); LowerMSCATTER() local
5786 EVT VT = Op->getValueType(0); LowerMLOAD() local
5810 LowerTruncateVectorStore(SDLoc DL,StoreSDNode * ST,EVT VT,EVT MemVT,SelectionDAG & DAG) LowerTruncateVectorStore() argument
5851 EVT VT = Value.getValueType(); LowerSTORE() local
5977 EVT VT = Op->getValueType(0); LowerLOAD() local
6007 MVT VT = Op.getSimpleValueType(); LowerABS() local
6048 MVT VT = Op.getSimpleValueType(); LowerFunnelShift() local
6437 useSVEForFixedLengthVectorVT(EVT VT,bool OverrideNEON) const useSVEForFixedLengthVectorVT() argument
7132 isPassedInFPR(EVT VT) isPassedInFPR() argument
9022 EVT VT = Op.getValueType(); LowerFCOPYSIGN() local
9048 __anon5c8f63cd0c02(EVT VT, SDValue Op, SelectionDAG &DAG) LowerFCOPYSIGN() argument
9121 EVT VT = Op.getValueType(); LowerCTPOP_PARITY() local
9198 EVT VT = Op.getValueType(); LowerCTTZ() local
9211 EVT VT = Op.getValueType(); LowerMinMax() local
9257 EVT VT = Op.getValueType(); LowerBitreverse() local
9338 EVT VT = N->getValueType(0); performOrXorChainCombine() local
9386 EVT VT = Op.getValueType(); LowerSETCC() local
9462 EVT VT = LHS.getValueType(); LowerSETCCCARRY() local
9524 EVT VT = LHS.getValueType(); LowerSELECT_CC() local
9538 EVT VT = LHS.getValueType(); LowerSELECT_CC() local
9663 EVT VT = TVal.getValueType(); LowerSELECT_CC() local
9671 EVT VT = TVal.getValueType(); LowerSELECT_CC() local
10067 EVT VT = Op.getValueType(); LowerVAARG() local
10137 EVT VT = Op.getValueType(); LowerFRAMEADDR() local
10157 EVT VT = getPointerTy(DAG.getDataLayout()); LowerSPONENTRY() local
10169 getRegisterByName(const char * RegName,LLT VT,const MachineFunction & MF) const getRegisterByName() argument
10188 EVT VT = Op.getValueType(); LowerADDROFRETURNADDR() local
10204 EVT VT = Op.getValueType(); LowerRETURNADDR() local
10253 isFPImmLegal(const APFloat & Imm,EVT VT,bool OptForSize) const isFPImmLegal() argument
10298 EVT VT = Operand.getValueType(); getEstimate() local
10323 EVT VT = Op.getValueType(); getSqrtInputTest() local
10345 EVT VT = Operand.getValueType(); getSqrtEstimate() local
10375 EVT VT = Operand.getValueType(); getRecipEstimate() local
10456 getPredicateRegisterClass(PredicateConstraint Constraint,EVT VT) getPredicateRegisterClass() argument
10487 getReducedGprRegisterClass(ReducedGprConstraint Constraint,EVT VT) getReducedGprRegisterClass() argument
10912 EVT VT = V64Reg.getValueType(); WidenVector() local
10935 EVT VT = Op.getValueType(); ReconstructShuffleWithRuntimeMask() local
11028 EVT VT = Op.getValueType(); ReconstructShuffle() local
11322 isSingletonEXTMask(ArrayRef<int> M,EVT VT,unsigned & Imm) isSingletonEXTMask() argument
11405 isWideDUPMask(ArrayRef<int> M,EVT VT,unsigned BlockSize,unsigned & DupLaneOp) isWideDUPMask() argument
11478 isEXTMask(ArrayRef<int> M,EVT VT,bool & ReverseEXT,unsigned & Imm) isEXTMask() argument
11520 isREVMask(ArrayRef<int> M,EVT VT,unsigned BlockSize) isREVMask() argument
11545 isZIPMask(ArrayRef<int> M,EVT VT,unsigned & WhichResult) isZIPMask() argument
11561 isUZPMask(ArrayRef<int> M,EVT VT,unsigned & WhichResult) isUZPMask() argument
11574 isTRNMask(ArrayRef<int> M,EVT VT,unsigned & WhichResult) isTRNMask() argument
11590 isZIP_v_undef_Mask(ArrayRef<int> M,EVT VT,unsigned & WhichResult) isZIP_v_undef_Mask() argument
11609 isUZP_v_undef_Mask(ArrayRef<int> M,EVT VT,unsigned & WhichResult) isUZP_v_undef_Mask() argument
11628 isTRN_v_undef_Mask(ArrayRef<int> M,EVT VT,unsigned & WhichResult) isTRN_v_undef_Mask() argument
11680 isConcatMask(ArrayRef<int> Mask,EVT VT,bool SplitLHS) isConcatMask() argument
11702 EVT VT = Op.getValueType(); tryFormConcatFromShuffle() local
11784 EVT VT = OpLHS.getValueType(); GeneratePerfectShuffle() local
11832 EVT VT = OpLHS.getValueType(); GeneratePerfectShuffle() local
11981 constructDup(SDValue V,int Lane,SDLoc dl,EVT VT,unsigned Opcode,SelectionDAG & DAG) constructDup() argument
12043 isWideTypeMask(ArrayRef<int> M,EVT VT,SmallVectorImpl<int> & NewMask) isWideTypeMask() argument
12090 EVT VT = Op.getValueType(); tryWidenMaskForShuffle() local
12130 EVT VT = Op.getValueType(); tryToConvertShuffleOfTbl2ToTbl4() local
12172 EVT VT = Op.getValueType(); LowerZERO_EXTEND_VECTOR_INREG() local
12189 EVT VT = Op.getValueType(); LowerVECTOR_SHUFFLE() local
12364 EVT VT = Op.getValueType(); LowerSPLAT_VECTOR() local
12397 EVT VT = Op.getValueType(); LowerDUPQLane() local
12441 EVT VT = BVN->getValueType(0); resolveBuildVector() local
12466 EVT VT = Op.getValueType(); tryAdvSIMDModImm64() local
12486 EVT VT = Op.getValueType(); tryAdvSIMDModImm32() local
12539 EVT VT = Op.getValueType(); tryAdvSIMDModImm16() local
12585 EVT VT = Op.getValueType(); tryAdvSIMDModImm321s() local
12616 EVT VT = Op.getValueType(); tryAdvSIMDModImm8() local
12637 EVT VT = Op.getValueType(); tryAdvSIMDModImmFP() local
12674 EVT VT = Bvec->getValueType(0); isAllConstantBuildVector() local
12737 EVT VT = N->getValueType(0); tryLowerToSLI() local
12847 EVT VT = Op.getValueType(); LowerVectorOR() local
12890 EVT VT = Op.getValueType(); NormalizeBuildVector() local
12918 EVT VT = Op.getValueType(); ConstantBuildVector() local
12960 EVT VT = Op.getValueType(); LowerBUILD_VECTOR() local
13450 EVT VT = Op.getOperand(0).getValueType(); LowerINSERT_VECTOR_ELT() local
13480 EVT VT = Op.getOperand(0).getValueType(); LowerEXTRACT_VECTOR_ELT() local
13586 EVT VT = Op.getValueType(); LowerINSERT_SUBVECTOR() local
13698 EVT VT = Op.getValueType(); LowerDIV() local
13804 isVShiftLImm(SDValue Op,EVT VT,bool isLong,int64_t & Cnt) isVShiftLImm() argument
13815 isVShiftRImm(SDValue Op,EVT VT,bool isNarrow,int64_t & Cnt) isVShiftRImm() argument
13825 EVT VT = Op.getValueType(); LowerTRUNCATE() local
13849 EVT VT = Op.getValueType(); LowerVectorSRA_SRL_SHL() local
13906 EmitVectorComparison(SDValue LHS,SDValue RHS,AArch64CC::CondCode CC,bool NoNans,EVT VT,const SDLoc & dl,SelectionDAG & DAG) EmitVectorComparison() argument
14095 getVectorBitwiseReduce(unsigned Opcode,SDValue Vec,EVT VT,SDLoc DL,SelectionDAG & DAG) getVectorBitwiseReduce() argument
14279 MVT VT = Op.getSimpleValueType(); LowerATOMIC_LOAD_AND() local
14300 EVT VT = Node->getValueType(0); LowerWindowsDYNAMIC_STACKALLOC() local
14366 EVT VT = Node->getValueType(0); LowerInlineDYNAMIC_STACKALLOC() local
14410 EVT VT = Op.getValueType(); LowerAVG() local
14448 EVT VT = Op.getValueType(); LowerVSCALE() local
14464 const EVT VT = TLI.getMemValueType(DL, CI.getArgOperand(0)->getType()); setInfoSVEStN() local
14697 EVT VT = Extend.getValueType(); shouldRemoveRedundantExtend() local
16123 __anon5c8f63cd1b02(EVT VT, Align AlignCheck) getOptimalMemOpType() argument
16153 __anon5c8f63cd1c02(EVT VT, Align AlignCheck) getOptimalMemOpLLT() argument
16196 const EVT VT = AddNode.getValueType(); isMulAddWithConstProfitable() local
16340 generateFMAsInMachineCombiner(EVT VT,CodeGenOptLevel OptLevel) const generateFMAsInMachineCombiner() argument
16369 EVT VT = N->getValueType(0); isDesirableToCommuteWithShift() local
16428 EVT VT = N->getValueType(0); shouldFoldConstantShiftPairToMask() local
16479 EVT VT = N->getValueType(0); foldVectorXorShiftIntoCmp() local
16704 EVT VT = A.getValueType(); performUADDVAddCombine() local
16752 EVT VT = A.getValueType(); performUADDVZextCombine() local
16814 EVT VT = N->getValueType(0); BuildSDIVPow2() local
16837 EVT VT = N->getValueType(0); BuildSREMPow2() local
16949 EVT VT = BV.getValueType(); performBuildShuffleExtendCombine() local
17014 EVT VT = Mul->getValueType(0); performMulVectorExtendCombine() local
17033 EVT VT = N->getValueType(0); performMulVectorCmpZeroCombine() local
17081 EVT VT = N->getValueType(0); performMulCombine() local
17254 EVT VT = N->getValueType(0); performVectorCompareAndMaskUnaryOpCombine() local
17294 EVT VT = N->getValueType(0); performIntToFpCombine() local
17469 EVT VT = N->getValueType(0); tryCombineToBSL() local
17571 EVT VT = N->getValueType(0); performANDORCSELCombine() local
17642 EVT VT = N->getValueType(0); performORCombine() local
17718 __anon5c8f63cd2402(EVT VT) performSVEAndCombine() argument
17814 EVT VT = N->getValueType(0); performANDSETCCCombine() local
17851 EVT VT = N->getValueType(0); performANDCombine() local
17914 EVT VT = N->getValueType(0); performFADDCombine() local
17945 hasPairwiseAdd(unsigned Opcode,EVT VT,bool FullFP16) hasPairwiseAdd() argument
17990 EVT VT = N0.getValueType(); performFirstTrueTestVectorCombine() local
18056 EVT VT = N->getValueType(0); performExtractVectorEltCombine() local
18118 EVT VT = N->getValueType(0); performConcatVectorsCombine() local
18278 EVT VT = Op.getValueType(); performConcatVectorsCombine() local
18373 EVT VT = N->getValueType(0); performExtractSubvectorCombine() local
18496 MVT VT = N.getSimpleValueType(); tryExtendDUPToExtractHigh() local
18677 EVT VT = Op->getValueType(0); performSetccAddFolding() local
18684 EVT VT = N->getValueType(0); performAddUADDVCombine() local
18723 EVT VT = N->getValueType(0); performAddCSelIntoCSinc() local
18796 EVT VT = N->getValueType(0); performAddDotCombine() local
18823 EVT VT = Op.getValueType(); getNegatedInteger() local
18855 EVT VT = CSel.getValueType(); performNegCSelCombine() local
18877 MVT VT = N->getSimpleValueType(0); performAddSubLongCombine() local
18970 EVT VT = N->getValueType(0); foldADCToCINC() local
18983 EVT VT = N->getValueType(0); performVectorAddSubExtCombine() local
19017 EVT VT = N->getValueType(0); performBuildVectorCombine() local
19062 EVT VT = N->getValueType(0); performTruncateCombine() local
19123 EVT VT = N->getValueType(0); performAddCombineSubShift() local
19139 EVT VT = N->getValueType(0); performAddCombineForShiftedOperands() local
19194 EVT VT = N->getValueType(0); performSubAddMULCombine() local
19257 EVT VT = N->getValueType(0); performAddSubIntoVectorOp() local
19416 EVT VT = N->getValueType(0); performExtBinopLoadFold() local
19665 EVT VT = N->getValueType(0); tryCombineShiftImm() local
19751 EVT VT = N->getValueType(0); LowerSVEIntrinsicEXT() local
19784 EVT VT = N->getValueType(0); tryConvertSVEWideCompare() local
19838 getPTest(SelectionDAG & DAG,EVT VT,SDValue Pg,SDValue Op,AArch64CC::CondCode Cond) getPTest() argument
19969 EVT VT = N->getValueType(0); performIntrinsicCombine() local
20438 EVT VT = N->getValueType(0); performLD1Combine() local
20464 EVT VT = N->getValueType(0); performLDNT1Combine() local
20493 EVT VT = N->getValueType(0); performLD1ReplicateCombine() local
20569 EVT VT = StVal.getValueType(); replaceZeroVectorStore() local
20636 EVT VT = StVal.getValueType(); replaceSplatVectorStore() local
20696 EVT VT = StVal.getValueType(); splitStores() local
20793 EVT VT = N->getValueType(0); performUnpackCombine() local
20828 EVT VT = Srl->getValueType(0); trySimplifySrlAddToRshrnb() local
21093 auto VT = CC->getValueType(0).getHalfNumVectorElementsVT(*DAG.getContext()); performSunpkloCombine() local
21111 EVT VT = N->getValueType(0); performPostLD1Combine() local
21450 EVT VT = VecOp.getValueType(); combineBoolVectorAndTruncateStore() local
21490 __anon5c8f63cd2f02(EVT VT) performSTORECombine() argument
22353 EVT VT = Op->getValueType(0); foldCSELOfCSEL() local
22450 EVT VT = N->getValueType(0); performSETCCCombine() local
22524 EVT VT = N->getValueType(0); performFlagSettingCombine() local
22788 EVT VT = CmpLHS.getValueType(); performVSelectCombine() local
22906 EVT VT = N->getValueType(0); performDUPCombine() local
23306 auto VT = cast<VTSDNode>(N->getOperand(1))->getVT(); performSignExtendInRegCombine() local
23554 EVT VT = N->getValueType(0); performFPExtendCombine() local
23560 __anon5c8f63cd3102(EVT VT) performFPExtendCombine() argument
23590 EVT VT = N->getValueType(0); performBSPExpandForSVE() local
23609 EVT VT = N->getValueType(0); performDupLane128Combine() local
23806 EVT VT = N->getValueType(0); performScalarToVectorCombine() local
24290 EVT VT; getPreIndexedAddressParts() local
24310 EVT VT; getPostIndexedAddressParts() local
24336 EVT VT = N->getValueType(0); replaceBoolVectorBitcast() local
24364 EVT VT = N->getValueType(0); CustomNonLegalBITCASTResults() local
24378 EVT VT = N->getValueType(0); ReplaceBITCASTResults() local
24429 EVT VT = N->getValueType(0); ReplaceAddWithADDP() local
24497 EVT VT = N->getValueType(0); ReplaceExtractSubVectorResults() local
24899 EVT VT = N->getValueType(0); ReplaceNodeResults() local
25462 isIntDivCheap(EVT VT,AttributeList Attr) const isIntDivCheap() argument
25659 getContainerForFixedLengthVector(SelectionDAG & DAG,EVT VT) getContainerForFixedLengthVector() argument
25685 getPredicateForFixedLengthVector(SelectionDAG & DAG,SDLoc & DL,EVT VT) getPredicateForFixedLengthVector() argument
25729 getPredicateForScalableVector(SelectionDAG & DAG,SDLoc & DL,EVT VT) getPredicateForScalableVector() argument
25736 getPredicateForVector(SelectionDAG & DAG,SDLoc & DL,EVT VT) getPredicateForVector() argument
25744 convertToScalableVector(SelectionDAG & DAG,EVT VT,SDValue V) convertToScalableVector() argument
25755 convertFromScalableVector(SelectionDAG & DAG,EVT VT,SDValue V) convertFromScalableVector() argument
25771 EVT VT = Op.getValueType(); LowerFixedLengthVectorLoadToSVE() local
25829 EVT VT = Op.getValueType(); LowerFixedLengthVectorMLoadToSVE() local
25880 EVT VT = Store->getValue().getValueType(); LowerFixedLengthVectorStoreToSVE() local
25913 EVT VT = Store->getValue().getValueType(); LowerFixedLengthVectorMStoreToSVE() local
25928 EVT VT = Op.getValueType(); LowerFixedLengthVectorIntDivideToSVE() local
25993 EVT VT = Op.getValueType(); LowerFixedLengthVectorIntExtendToSVE() local
26029 EVT VT = Op.getValueType(); LowerFixedLengthVectorTruncateToSVE() local
26065 EVT VT = Op.getValueType(); LowerFixedLengthExtractVectorElt() local
26078 EVT VT = Op.getValueType(); LowerFixedLengthInsertVectorElt() local
26098 EVT VT = Op.getValueType(); LowerToPredicatedOp() local
26154 EVT VT = Op.getValueType(); LowerToScalableOp() local
26214 EVT VT = ReduceOp.getValueType(); LowerPredReductionToSVE() local
26288 EVT VT = Op.getValueType(); LowerFixedLengthVectorSelectToSVE() local
26339 EVT VT = Op.getValueType(); LowerFixedLengthBitcastToSVE() local
26359 EVT VT = Op.getValueType(); LowerFixedLengthConcatVectorsToSVE() local
26386 EVT VT = Op.getValueType(); LowerFixedLengthFPExtendToSVE() local
26411 EVT VT = Op.getValueType(); LowerFixedLengthFPRoundToSVE() local
26435 EVT VT = Op.getValueType(); LowerFixedLengthIntToFPToSVE() local
26507 EVT VT = Op.getValueType(); LowerFixedLengthFPToIntToSVE() local
26548 GenerateFixedLengthSVETBL(SDValue Op,SDValue Op1,SDValue Op2,ArrayRef<int> ShuffleMask,EVT VT,EVT ContainerVT,SelectionDAG & DAG) GenerateFixedLengthSVETBL() argument
26623 EVT VT = Op.getValueType(); LowerFixedLengthVECTOR_SHUFFLEToSVE() local
26777 getSVESafeBitCast(EVT VT,SDValue Op,SelectionDAG & DAG) const getSVESafeBitCast() argument
27078 getVectorTypeBreakdownForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) const getVectorTypeBreakdownForCallingConv() argument
[all...]
H A DAArch64ISelDAGToDAG.cpp183 if (ShtAmt > VT.getScalarSizeInBits() / 2 || Op.getOpcode() != ISD::ADD) in SelectRoundingVLShr() local
169 EVT VT = N->getValueType(0); SelectExtractHigh() local
704 EVT VT = N.getValueType(); SelectShiftedRegisterFromAnd() local
1445 EVT VT = N->getValueType(0); SelectTable() local
1467 EVT VT = LD->getMemoryVT(); tryIndexedLoad() local
1567 EVT VT = N->getValueType(0); SelectLoad() local
1596 EVT VT = N->getValueType(0); SelectPostLoad() local
1660 SelectOpcodeFromVT(EVT VT,ArrayRef<unsigned> Opcodes) SelectOpcodeFromVT() argument
1715 EVT VT = N->getValueType(0); SelectPExtPair() local
1729 EVT VT = N->getValueType(0); SelectWhilePair() local
1745 EVT VT = N->getValueType(0); SelectCVTIntrinsic() local
1766 EVT VT = N->getValueType(0); SelectDestructiveMultiIntrinsic() local
1802 EVT VT = N->getValueType(0); SelectPredicatedLoad() local
1837 EVT VT = N->getValueType(0); SelectContiguousMultiVectorLoad() local
1884 EVT VT = Node->getValueType(0); SelectMultiVectorLuti() local
1903 EVT VT = N->getValueType(0); SelectClamp() local
1972 EVT VT = N->getValueType(0); SelectMultiVectorMove() local
1988 EVT VT = N->getValueType(0); SelectUnaryMultiIntrinsic() local
2016 EVT VT = N->getOperand(2)->getValueType(0); SelectStore() local
2078 EVT VT = N->getOperand(2)->getValueType(0); SelectPostStore() local
2106 EVT VT = V64Reg.getValueType(); operator ()() local
2122 EVT VT = V128Reg.getValueType(); NarrowVector() local
2134 EVT VT = N->getValueType(0); SelectLoadLane() local
2172 EVT VT = N->getValueType(0); SelectPostLoadLane() local
2226 EVT VT = N->getOperand(2)->getValueType(0); SelectStoreLane() local
2254 EVT VT = N->getOperand(2)->getValueType(0); SelectPostStoreLane() local
2292 EVT VT = N->getValueType(0); isBitfieldExtractOpFromAnd() local
2383 EVT VT = N->getValueType(0); isBitfieldExtractOpFromSExtInReg() local
2457 EVT VT = N->getValueType(0); isBitfieldExtractOpFromShr() local
2521 EVT VT = N->getValueType(0); tryBitfieldExtractOpFromSExt() local
2589 EVT VT = N->getValueType(0); tryBitfieldExtractOp() local
2616 isBitfieldDstMask(uint64_t DstMask,const APInt & BitsToBeInserted,unsigned NumberOfIgnoredHighBits,EVT VT) isBitfieldDstMask() argument
2853 EVT VT = Op.getValueType(); getLeftShift() local
2896 EVT VT = Op.getValueType(); isBitfieldPositioningOp() local
2930 EVT VT = Op.getValueType(); isBitfieldPositioningOpFromAnd() local
3052 EVT VT = Op.getValueType(); isBitfieldPositioningOpFromShl() local
3077 isShiftedMask(uint64_t Mask,EVT VT) isShiftedMask() argument
3089 EVT VT = N->getValueType(0); tryBitfieldInsertOpFromOrAndImm() local
3181 EVT VT = Dst.getValueType(); isWorthFoldingIntoOrrWithShift() local
3252 EVT VT = N->getValueType(0); tryOrrWithShift() local
3353 EVT VT = N->getValueType(0); tryBitfieldInsertOpFromOr() local
3423 EVT VT = OrOpd1Val.getValueType(); tryBitfieldInsertOpFromOr() local
3549 EVT VT = N->getValueType(0); tryBitfieldInsertInZeroOp() local
3575 EVT VT = N->getValueType(0); tryShiftAmountMod() local
3972 SelectSVEAddSubImm(SDValue N,MVT VT,SDValue & Imm,SDValue & Shift) SelectSVEAddSubImm() argument
4012 SelectSVECpyDupImm(SDValue N,MVT VT,SDValue & Imm,SDValue & Shift) SelectSVECpyDupImm() argument
4064 SelectSVEArithImm(SDValue N,MVT VT,SDValue & Imm) SelectSVEArithImm() argument
4092 SelectSVELogicalImm(SDValue N,MVT VT,SDValue & Imm,bool Invert) SelectSVELogicalImm() argument
4223 EVT VT = N->getValueType(0); trySelectCastFixedLengthToScalableVector() local
4252 EVT VT = N->getValueType(0); trySelectCastScalableToFixedLengthVector() local
4278 EVT VT = N->getValueType(0); trySelectXAR() local
4368 EVT VT = Node->getValueType(0); Select() local
7016 EVT VT = N.getValueType(); SelectAnyPredicate() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp64 MVT VT = N->getSimpleValueType(0); PreprocessISelDAG() local
81 MVT VT = N->getSimpleValueType(0); PreprocessISelDAG() local
176 selectImmSeq(SelectionDAG * CurDAG,const SDLoc & DL,const MVT VT,RISCVMatInt::InstSeq & Seq) selectImmSeq() argument
205 selectImm(SelectionDAG * CurDAG,const SDLoc & DL,const MVT VT,int64_t Imm,const RISCVSubtarget & Subtarget) selectImm() argument
344 MVT VT = Node->getSimpleValueType(0); selectVLSEG() local
383 MVT VT = Node->getSimpleValueType(0); selectVLSEGFF() local
426 MVT VT = Node->getSimpleValueType(0); selectVLXSEG() local
481 MVT VT = Node->getOperand(2)->getSimpleValueType(0); selectVSSEG() local
511 MVT VT = Node->getOperand(2)->getSimpleValueType(0); selectVSXSEG() local
607 MVT VT = Node->getSimpleValueType(0); tryShrinkShlLogicImm() local
698 __anon6ef9331d0102(SDValue N0, unsigned Msb, unsigned Lsb, SDLoc DL, MVT VT) trySignedBitfieldExtract() argument
705 MVT VT = Node->getSimpleValueType(0); trySignedBitfieldExtract() local
833 MVT VT = Node->getSimpleValueType(0); Select() local
1128 __anon6ef9331d0202(SDNode *Node, SDLoc DL, MVT VT, SDValue X, unsigned Msb, unsigned Lsb) Select() argument
1715 MVT VT = Node->getSimpleValueType(0); Select() local
1759 MVT VT = Node->getSimpleValueType(0); Select() local
1800 MVT VT = Node->getSimpleValueType(0); Select() local
1913 MVT VT = Node->getOperand(2)->getSimpleValueType(0); Select() local
1957 MVT VT = Node->getOperand(2)->getSimpleValueType(0); Select() local
2259 selectConstantAddr(SelectionDAG * CurDAG,const SDLoc & DL,const MVT VT,const RISCVSubtarget * Subtarget,SDValue Addr,SDValue & Base,SDValue & Offset,bool IsPrefetch=false) selectConstantAddr() argument
2317 EVT VT = cast<MemSDNode>(Use)->getMemoryVT(); isWorthFoldingAdd() local
2337 EVT VT = Addr.getSimpleValueType(); SelectAddrRegRegScale() local
2379 EVT VT = Addr.getValueType(); SelectAddrRegRegScale() local
2393 MVT VT = Addr.getSimpleValueType(); SelectAddrRegImm() local
2487 MVT VT = Addr.getSimpleValueType(); SelectAddrRegImmLsb00000() local
2593 EVT VT = ShAmt.getValueType(); selectShiftMask() local
2605 EVT VT = ShAmt.getValueType(); selectShiftMask() local
2701 MVT VT = N.getSimpleValueType(); selectSExtBits() local
2718 MVT VT = N.getSimpleValueType(); selectZExtBits() local
2756 EVT VT = N.getValueType(); selectSHXADDOp() local
2768 EVT VT = N.getValueType(); selectSHXADDOp() local
2797 EVT VT = N.getValueType(); selectSHXADDOp() local
2809 EVT VT = N.getValueType(); selectSHXADDOp() local
2846 EVT VT = N.getValueType(); selectSHXADD_UWOp() local
3220 MVT VT = CFP->getSimpleValueType(0); selectFPImm() local
[all...]
H A DRISCVISelLowering.cpp189 addRegClassForRVV(VT); in RISCVTargetLowering() local
164 __anonbba6e2090102(MVT VT) RISCVTargetLowering() argument
187 for (MVT VT : BoolVecVTs) RISCVTargetLowering() local
197 for (MVT VT : F16VecVTs) RISCVTargetLowering() local
201 for (MVT VT : BF16VecVTs) RISCVTargetLowering() local
205 for (MVT VT : F32VecVTs) RISCVTargetLowering() local
209 for (MVT VT : F64VecVTs) RISCVTargetLowering() local
213 __anonbba6e2090202(MVT VT) RISCVTargetLowering() argument
219 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) RISCVTargetLowering() local
223 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) RISCVTargetLowering() local
717 for (MVT VT : BoolVecVTs) { RISCVTargetLowering() local
784 for (MVT VT : IntVecVTs) { RISCVTargetLowering() local
935 __anonbba6e2090302(MVT VT) RISCVTargetLowering() argument
1012 __anonbba6e2090402(MVT VT, ArrayRef<MVT::SimpleValueType> SmallerVTs) RISCVTargetLowering() argument
1020 for (MVT VT : F16VecVTs) { RISCVTargetLowering() local
1026 for (MVT VT : F16VecVTs) { RISCVTargetLowering() local
1060 for (MVT VT : F32VecVTs) { RISCVTargetLowering() local
1069 for (MVT VT : F64VecVTs) { RISCVTargetLowering() local
1079 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { RISCVTargetLowering() local
1226 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { RISCVTargetLowering() local
1835 EVT VT = Y.getValueType(); hasAndNotCompare() local
2102 isFPImmLegal(const APFloat & Imm,EVT VT,bool ForCodeSize) const isFPImmLegal() argument
2202 getVectorTypeBreakdownForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) const getVectorTypeBreakdownForCallingConv() argument
2282 getLMUL(MVT VT) getLMUL() argument
2326 getSubregIndexByMVT(MVT VT,unsigned Index) getSubregIndexByMVT() argument
2349 getRegClassIDForVecVT(MVT VT) getRegClassIDForVecVT() argument
2439 useRVVForFixedLengthVectorVT(MVT VT,const RISCVSubtarget & Subtarget) useRVVForFixedLengthVectorVT() argument
2511 getContainerForFixedLengthVector(const TargetLowering & TLI,MVT VT,const RISCVSubtarget & Subtarget) getContainerForFixedLengthVector() argument
2545 getContainerForFixedLengthVector(SelectionDAG & DAG,MVT VT,const RISCVSubtarget & Subtarget) getContainerForFixedLengthVector() argument
2556 convertToScalableVector(EVT VT,SDValue V,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) convertToScalableVector() argument
2568 convertFromScalableVector(EVT VT,SDValue V,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) convertFromScalableVector() argument
2676 shouldExpandBuildVectorWithShuffles(EVT VT,unsigned DefinedValues) const shouldExpandBuildVectorWithShuffles() argument
2870 MVT VT = Op.getSimpleValueType(); lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() local
2980 MVT VT = Op.getSimpleValueType(); lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() local
3080 MVT VT = Op.getSimpleValueType(); lowerFTRUNC_FCEIL_FFLOOR_FROUND() local
3108 MVT VT = Op.getSimpleValueType(); lowerVectorXRINT() local
3132 getVSlidedown(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlidedown() argument
3144 getVSlideup(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlideup() argument
3154 getLMUL1VT(MVT VT) getLMUL1VT() argument
3303 matchSplatAsGather(SDValue SplatVal,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) matchSplatAsGather() argument
3347 MVT VT = Op.getSimpleValueType(); lowerBuildVectorViaDominantValues() local
3454 MVT VT = Op.getSimpleValueType(); lowerBuildVectorOfConstants() local
3755 MVT VT = Op.getSimpleValueType(); lowerBUILD_VECTOR() local
3929 splatPartsI64WithVL(const SDLoc & DL,MVT VT,SDValue Passthru,SDValue Lo,SDValue Hi,SDValue VL,SelectionDAG & DAG) splatPartsI64WithVL() argument
3986 splatSplitI64WithVL(const SDLoc & DL,MVT VT,SDValue Passthru,SDValue Scalar,SDValue VL,SelectionDAG & DAG) splatSplitI64WithVL() argument
3999 lowerScalarSplat(SDValue Passthru,SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarSplat() argument
4036 lowerScalarInsert(SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarInsert() argument
4096 isDeinterleaveShuffle(MVT VT,MVT ContainerVT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget) isDeinterleaveShuffle() argument
4141 isInterleaveShuffle(ArrayRef<int> Mask,MVT VT,int & EvenSrc,int & OddSrc,const RISCVSubtarget & Subtarget) isInterleaveShuffle() argument
4251 getDeinterleaveViaVNSRL(const SDLoc & DL,MVT VT,SDValue Src,bool EvenElts,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) getDeinterleaveViaVNSRL() argument
4310 lowerVECTOR_SHUFFLEAsVSlidedown(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlidedown() argument
4387 lowerVECTOR_SHUFFLEAsVSlideup(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlideup() argument
4431 lowerVECTOR_SHUFFLEAsVSlide1(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlide1() argument
4573 MVT VT = SVN->getSimpleValueType(0); lowerBitreverseShuffle() local
4629 EVT VT = SVN->getValueType(0); lowerVECTOR_SHUFFLEAsRotate() local
4664 MVT VT = SVN->getSimpleValueType(0); lowerShuffleViaVRegSplitting() local
4742 MVT VT = Op.getSimpleValueType(); lowerVECTOR_SHUFFLE() local
5118 MVT VT = Op.getSimpleValueType(); lowerCTLZ_CTTZ_ZERO_UNDEF() local
5247 MVT VT = Op.getSimpleValueType(); expandUnalignedRVVLoad() local
5278 MVT VT = StoredVal.getSimpleValueType(); expandUnalignedRVVStore() local
5364 MVT VT = Op.getSimpleValueType(); LowerIS_FPCLASS() local
5466 MVT VT = Op.getSimpleValueType(); lowerFMAXIMUM_FMINIMUM() local
5885 EVT VT = Op.getValueType(); LowerOperation() local
5968 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6003 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6024 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6080 EVT VT = Op.getValueType(); LowerOperation() local
6097 EVT VT = Op.getValueType(); LowerOperation() local
6160 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6309 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6445 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6485 EVT VT = Op.getValueType(); LowerOperation() local
6498 MVT VT = Op.getSimpleValueType(); LowerOperation() local
7063 MVT VT = N->getSimpleValueType(0); combineSelectToBinOp() local
7156 EVT VT = BO->getValueType(0); foldBinOpIntoSelectIfProfitable() local
7187 MVT VT = Op.getSimpleValueType(); lowerSELECT() local
7383 EVT VT = Op.getValueType(); lowerFRAMEADDR() local
7409 EVT VT = Op.getValueType(); lowerRETURNADDR() local
7433 EVT VT = Lo.getValueType(); lowerShiftLeftParts() local
7472 EVT VT = Lo.getValueType(); lowerShiftRightParts() local
7523 MVT VT = Op.getSimpleValueType(); lowerVectorMaskSplat() local
7620 MVT VT = Op.getOperand(0).getSimpleValueType(); lowerFixedLengthVectorExtendToRVV() local
7701 MVT VT = Op.getSimpleValueType(); lowerVectorTruncLike() local
7764 MVT VT = Op.getSimpleValueType(); lowerStrictFPExtendOrRoundLike() local
7816 MVT VT = Op.getSimpleValueType(); lowerVectorFPExtendOrRoundLike() local
8280 MVT VT = Op.getOperand(SplatOp - 1).getSimpleValueType(); lowerVectorIntrinsicScalars() local
8474 isValidEGW(int EGS,EVT VT,const RISCVSubtarget & Subtarget) isValidEGW() argument
8621 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_WO_CHAIN() local
8701 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_WO_CHAIN() local
8745 MVT VT = Op->getSimpleValueType(0); LowerINTRINSIC_W_CHAIN() local
8822 MVT VT = Op->getSimpleValueType(0); LowerINTRINSIC_W_CHAIN() local
8860 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_W_CHAIN() local
8910 MVT VT = Val.getSimpleValueType(); LowerINTRINSIC_VOID() local
8958 MVT VT = Op->getOperand(2).getSimpleValueType(); LowerINTRINSIC_VOID() local
9659 MVT VT = N.getSimpleValueType(); widenVectorOpsToi8() local
9856 MVT VT = Op.getSimpleValueType(); lowerSTEP_VECTOR() local
10002 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorLoadToRVV() local
10050 MVT VT = StoreVal.getSimpleValueType(); lowerFixedLengthVectorStoreToRVV() local
10091 MVT VT = Op.getSimpleValueType(); lowerMaskedLoad() local
10176 MVT VT = Val.getSimpleValueType(); lowerMaskedStore() local
10212 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorSetccToRVV() local
10240 MVT VT = Op.getSimpleValueType(); lowerVectorStrictFSetcc() local
10322 MVT VT = Op.getSimpleValueType(); lowerABS() local
10360 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorFCOPYSIGNToRVV() local
10380 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorSelectToRVV() local
10408 MVT VT = Op.getSimpleValueType(); lowerToScalableOp() local
10461 MVT VT = Op.getSimpleValueType(); lowerVPOp() local
10514 MVT VT = Op.getSimpleValueType(); lowerVPExtMaskOp() local
10547 MVT VT = Op.getSimpleValueType(); lowerVPSetCCMaskOp() local
10751 MVT VT = Op.getSimpleValueType(); lowerVPFPIntConvOp() local
10770 MVT VT = Op.getSimpleValueType(); lowerVPSpliceExperimental() local
10842 MVT VT = Op.getSimpleValueType(); lowerVPReverseExperimental() local
10961 MVT VT = Op.getSimpleValueType(); lowerLogicVPOp() local
10989 MVT VT = Op.getSimpleValueType(); lowerVPStridedLoad() local
11038 MVT VT = StoreVal.getSimpleValueType(); lowerVPStridedStore() local
11077 MVT VT = Op.getSimpleValueType(); lowerMaskedGather() local
11202 MVT VT = Val.getSimpleValueType(); lowerMaskedScatter() local
11623 MVT VT = N->getSimpleValueType(0); ReplaceNodeResults() local
11777 EVT VT = N->getValueType(0); ReplaceNodeResults() local
11818 MVT VT = N->getSimpleValueType(0); ReplaceNodeResults() local
11983 EVT VT = N->getValueType(0); ReplaceNodeResults() local
12103 const EVT VT = N->getValueType(0); combineBinOpOfExtractToReduceTree() local
12297 EVT VT = N->getValueType(0); transformAddShlImm() local
12349 EVT VT = N->getValueType(0); combineSelectAndUse() local
12444 EVT VT = N->getValueType(0); transformAddImmMulImm() local
12494 EVT VT = N->getValueType(0); combineAddOfBooleanXor() local
12537 EVT VT = N->getValueType(0); combineSubOfBoolean() local
12586 EVT VT = N->getValueType(0); performSUBCombine() local
12629 EVT VT = N->getValueType(0); combineDeMorganOfBoolean() local
12649 EVT VT = N->getValueType(0); performTRUNCATECombine() local
12735 EVT VT = N->getValueType(0); combineOrOfCZERO() local
12809 EVT VT = N0.getValueType(); performXORCombine() local
12829 EVT VT = N->getValueType(0); performMULCombine() local
12878 EVT VT = N.getValueType(); narrowIndex() local
12944 EVT VT = N->getValueType(0); performSETCCCombine() local
12990 EVT VT = N->getValueType(0); performSIGN_EXTEND_INREGCombine() local
13113 MVT VT = Root->getSimpleValueType(0); getNarrowType() local
13193 MVT VT = OrigOperand.getSimpleValueType(); fillUpExtensionSupport() local
13246 MVT VT = Root->getSimpleValueType(0); fillUpExtensionSupport() local
13350 MVT VT = Root->getSimpleValueType(0); getMaskAndVL() local
13869 EVT VT = N->getValueType(0); performFP_TO_INTCombine() local
14015 EVT VT = N->getValueType(0); performBITREVERSECombine() local
14401 EVT VT = Cond.getValueType(); tryDemorganOfBooleanCondition() local
14560 EVT VT = N->getValueType(0); tryFoldSelectIntoOp() local
14644 EVT VT = N->getValueType(0); useInversedSetcc() local
14696 EVT VT = N->getValueType(0); performBUILD_VECTORCombine() local
14752 EVT VT = InVec.getValueType(); performINSERT_VECTOR_ELTCombine() local
14821 EVT VT = N->getValueType(0); performCONCAT_VECTORSCombine() local
15013 EVT VT = N->getValueType(0); combineToVWMACC() local
15052 matchIndexAsShuffle(EVT VT,SDValue Index,SDValue Mask,SmallVector<int> & ShuffleMask) matchIndexAsShuffle() argument
15087 matchIndexAsWiderOp(EVT VT,SDValue Index,SDValue Mask,Align BaseAlign,const RISCVSubtarget & ST) matchIndexAsWiderOp() argument
15230 MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
15403 EVT VT = N->getValueType(0); PerformDAGCombine() local
15518 EVT VT = N->getValueType(0); PerformDAGCombine() local
15543 const EVT VT = N->getValueType(0); PerformDAGCombine() local
15664 EVT VT = MSN->getValue()->getValueType(0); PerformDAGCombine() local
15734 EVT VT = N->getValueType(0); PerformDAGCombine() local
15752 EVT VT = N->getValueType(0); PerformDAGCombine() local
15889 EVT VT = N->getValueType(0); PerformDAGCombine() local
15911 const MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
15922 const MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
15954 EVT VT = N->getValueType(0); PerformDAGCombine() local
15965 const MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
16014 MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
16062 EVT VT = N->getValueType(0); PerformDAGCombine() local
16073 EVT VT = N->getValueType(0); PerformDAGCombine() local
16173 EVT VT = Op.getValueType(); targetShrinkDemandedConstant() local
18305 getPrefTypeAlign(EVT VT,SelectionDAG & DAG) getPrefTypeAlign() argument
18624 MVT VT = Outs[i].VT; CanLowerReturn() local
19609 EVT VT; getPreIndexedAddressParts() local
19632 EVT VT; getPostIndexedAddressParts() local
19708 decomposeMulByConstant(LLVMContext & Context,EVT VT,SDValue C) const decomposeMulByConstant() argument
19751 EVT VT = AddNode.getValueType(); isMulAddWithConstProfitable() local
19772 allowsMisalignedMemoryAccesses(EVT VT,unsigned AddrSpace,Align Alignment,MachineMemOperand::Flags Flags,unsigned * Fast) const allowsMisalignedMemoryAccesses() argument
19943 isIntDivCheap(EVT VT,AttributeList Attr) const isIntDivCheap() argument
19980 EVT VT = getValueType(DL, VTy); isLegalInterleavedAccessType() local
20257 getRegisterByName(const char * RegName,LLT VT,const MachineFunction & MF) const getRegisterByName() argument
20332 getCustomCtpopCost(EVT VT,ISD::CondCode Cond) const getCustomCtpopCost() argument
20373 EVT VT = N->getValueType(0); BuildSDIVPow2() local
20384 shouldFoldSelectWithSingleBitTest(EVT VT,const APInt & AndMask) const shouldFoldSelectWithSingleBitTest() argument
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp42 MVT VT = Node->getSimpleValueType(0); INITIALIZE_PASS() local
204 MVT VT = Addr.getSimpleValueType(); SelectAddrConstant() local
270 EVT VT = N.getValueType(); selectShiftMask() local
297 MVT VT = N.getSimpleValueType(); selectSExti32() local
314 MVT VT = N.getSimpleValueType(); selectZExti32() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp40 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType() argument
147 for (MVT VT : MVT::integer_valuetypes()) AMDGPUTargetLowering() local
151 for (MVT VT : MVT::integer_valuetypes()) { AMDGPUTargetLowering() local
163 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) AMDGPUTargetLowering() local
410 for (MVT VT : ScalarIntVTs) { AMDGPUTargetLowering() local
456 for (MVT VT : VectorIntTypes) { AMDGPUTargetLowering() local
477 for (MVT VT : FloatVectorTypes) { AMDGPUTargetLowering() local
657 opMustUseVOP3Encoding(const SDNode * N,MVT VT) opMustUseVOP3Encoding() argument
718 MVT VT = N->getValueType(0).getScalarType().getSimpleVT(); allUsesHaveSourceMods() local
736 getTypeForExtReturn(LLVMContext & Context,EVT VT,ISD::NodeType ExtendKind) const getTypeForExtReturn() argument
757 isFPImmLegal(const APFloat & Imm,EVT VT,bool ForCodeSize) const isFPImmLegal() argument
881 EVT VT = Op.getValueType(); getNegatedExpression() local
1471 EVT VT = Op.getValueType(); LowerCONCAT_VECTORS() local
1506 EVT VT = Op.getValueType(); LowerEXTRACT_SUBVECTOR() local
1555 combineFMinMaxLegacyImpl(const SDLoc & DL,EVT VT,SDValue LHS,SDValue RHS,SDValue True,SDValue False,SDValue CC,DAGCombinerInfo & DCI) const combineFMinMaxLegacyImpl() argument
1623 combineFMinMaxLegacy(const SDLoc & DL,EVT VT,SDValue LHS,SDValue RHS,SDValue True,SDValue False,SDValue CC,DAGCombinerInfo & DCI) const combineFMinMaxLegacy() argument
1696 getSplitDestVTs(const EVT & VT,SelectionDAG & DAG) const getSplitDestVTs() argument
1729 EVT VT = Op.getValueType(); SplitVectorLoad() local
1789 EVT VT = Op.getValueType(); WidenOrSplitVectorLoad() local
1824 EVT VT = Val.getValueType(); SplitVectorStore() local
1867 EVT VT = Op.getValueType(); LowerDIVREM24() local
1983 EVT VT = Op.getValueType(); LowerUDIVREM64() local
2196 EVT VT = Op.getValueType(); LowerUDIVREM() local
2251 EVT VT = Op.getValueType(); LowerSDIVREM() local
2311 EVT VT = Op.getValueType(); LowerFREM() local
2447 auto VT = Op.getValueType(); LowerFRINT() local
2460 EVT VT = Op.getValueType(); LowerFROUND() local
2554 EVT VT = Src.getValueType(); getIsLtSmallestNormal() local
2571 EVT VT = Src.getValueType(); getIsFinite() local
2590 MVT VT = MVT::f32; getScaledLogInput() local
2616 EVT VT = Op.getValueType(); LowerFLOG2() local
2643 getMad(SelectionDAG & DAG,const SDLoc & SL,EVT VT,SDValue X,SDValue Y,SDValue C,SDNodeFlags Flags=SDNodeFlags ()) getMad() argument
2652 EVT VT = Op.getValueType(); LowerFLOGCommon() local
2755 EVT VT = Src.getValueType(); LowerFLOGUnsafe() local
2796 EVT VT = Op.getValueType(); lowerFEXP2() local
2845 EVT VT = X.getValueType(); lowerFEXPUnsafe() local
2885 const EVT VT = X.getValueType(); lowerFEXP10Unsafe() local
2935 EVT VT = Op.getValueType(); lowerFEXP() local
3616 MVT VT = Op.getSimpleValueType(); LowerSIGN_EXTEND_INREG() local
3645 EVT VT = Op.getValueType(); isI24() local
3757 EVT VT = LN->getMemoryVT(); performLoadCombine() local
3808 EVT VT = SN->getMemoryVT(); performStoreCombine() local
3940 EVT VT = N->getValueType(0); performShlCombine() local
4047 EVT VT = N->getValueType(0); performSrlCombine() local
4093 EVT VT = N->getValueType(0); performTruncateCombine() local
4210 EVT VT = N->getValueType(0); performMulCombine() local
4341 EVT VT = N->getValueType(0); performMulhsCombine() local
4374 EVT VT = N->getValueType(0); performMulhuCombine() local
4409 EVT VT = Op.getValueType(); getFFBX_U32() local
4473 EVT VT = N1.getValueType(); distributeOpThroughSelect() local
4496 EVT VT = N.getValueType(); foldFreeOpFromSelect() local
4575 EVT VT = N->getValueType(0); performSelectCombine() local
4695 EVT VT = N->getValueType(0); performFNegCombine() local
5203 EVT VT = N->getValueType(0); PerformDAGCombine() local
5239 CreateLiveInRegister(SelectionDAG & DAG,const TargetRegisterClass * RC,Register Reg,EVT VT,const SDLoc & SL,bool RawReg) const CreateLiveInRegister() argument
5274 loadStackInputValue(SelectionDAG & DAG,EVT VT,const SDLoc & SL,int64_t Offset) const loadStackInputValue() argument
5310 loadInputValue(SelectionDAG & DAG,const TargetRegisterClass * RC,EVT VT,const SDLoc & SL,const ArgDescriptor & Arg) const loadInputValue() argument
5525 EVT VT = Operand.getValueType(); getSqrtEstimate() local
5541 EVT VT = Operand.getValueType(); getRecipEstimate() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp391 ARMMoveToFPReg(MVT VT,unsigned SrcReg) ARMMoveToFPReg() argument
401 ARMMoveToIntReg(MVT VT,unsigned SrcReg) ARMMoveToIntReg() argument
414 ARMMaterializeFP(const ConstantFP * CFP,MVT VT) ARMMaterializeFP() argument
453 ARMMaterializeInt(const Constant * C,MVT VT) ARMMaterializeInt() argument
522 ARMMaterializeGV(const GlobalValue * GV,MVT VT) ARMMaterializeGV() argument
629 MVT VT = CEVT.getSimpleVT(); fastMaterializeConstant() local
647 MVT VT; fastMaterializeAlloca() local
671 isTypeLegal(Type * Ty,MVT & VT) isTypeLegal() argument
683 isLoadTypeLegal(Type * Ty,MVT & VT) isLoadTypeLegal() argument
800 ARMSimplifyAddress(Address & Addr,MVT VT,bool useAM3) ARMSimplifyAddress() argument
852 AddLoadStoreOperands(MVT VT,Address & Addr,const MachineInstrBuilder & MIB,MachineMemOperand::Flags Flags,bool useAM3) AddLoadStoreOperands() argument
898 ARMEmitLoad(MVT VT,Register & ResultReg,Address & Addr,MaybeAlign Alignment,bool isZExt,bool allocReg) ARMEmitLoad() argument
1025 MVT VT; SelectLoad() local
1040 ARMEmitStore(MVT VT,unsigned SrcReg,Address & Addr,MaybeAlign Alignment) ARMEmitStore() argument
1159 MVT VT; SelectStore() local
1603 MVT VT; SelectSelect() local
1679 MVT VT; SelectDiv() local
1708 MVT VT; SelectRem() local
1779 MVT VT = FPVT.getSimpleVT(); SelectBinaryFPOp() local
2449 MVT VT; ARMTryEmitSmallMemCpy() local
2919 MVT VT; tryToFoldLoadIntoMI() local
2955 ARMLowerPICELF(const GlobalValue * GV,MVT VT) ARMLowerPICELF() argument
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/WebAssembly/AsmParser/
H A DWebAssemblyAsmTypeCheck.cpp159 for (auto VT : llvm::reverse(LastSig.Returns)) { in checkEnd() local
174 for (auto VT : llvm::reverse(Sig.Params)) in checkSig() local
404 auto VT = WebAssembly::regClassToValType(Op.RegClass); typeCheck() local
413 auto VT = WebAssembly::regClassToValType(Op.RegClass); typeCheck() local
[all...]

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