| /llvm-project/llvm/lib/CodeGen/ |
| H A D | SwiftErrorValueTracking.cpp | 37 auto VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVReg() local
46 const Value *Val, Register VReg) { in setCurrentVReg() argument
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVRegDefAt() local
72 Register VReg = getOrCreateVReg(MBB, Val); getOrCreateVRegUseAt() local
133 Register VReg = MF->getRegInfo().createVirtualRegister(RC); createEntriesInEntryBlock() local
261 Register VReg = Use.second; propagateVRegs() local
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| H A D | MIRVRegNamerUtils.cpp | 49 VRM[Reg] = createVirtualRegisterWithLowerName(Reg, GetUniqueVRegName(VReg)); in getVRegRenameMap() local
141 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg)); in createVirtualRegister() argument
168 createVirtualRegisterWithLowerName(unsigned VReg,StringRef Name) createVirtualRegisterWithLowerName() argument
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| H A D | LiveRangeEdit.cpp | 36 Register VReg = MRI.cloneVirtualRegister(OldReg); in createEmptyIntervalFrom() local
56 Register VReg = MRI.cloneVirtualRegister(OldReg); in createFrom() local
453 Register VReg = LI->reg(); eliminateDeadDefs() local
489 MRI_NoteNewVirtualRegister(Register VReg) MRI_NoteNewVirtualRegister() argument
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| H A D | RegAllocPBQP.cpp | 333 LiveInterval &LI = LIS.getInterval(VReg); in apply() local
604 Register VReg = Worklist.back(); initializeGraph() local
663 auto VReg = KV.first; initializeGraph() local
690 spillVReg(Register VReg,SmallVectorImpl<Register> & NewIntervals,MachineFunction & MF,LiveIntervals & LIS,VirtRegMap & VRM,Spiller & VRegSpiller) spillVReg() argument
734 Register VReg = G.getNodeMetadata(NId).getVReg(); mapPBQPToRegAlloc() local
893 Register VReg = G.getNodeMetadata(NId).getVReg(); PrintNodeInfo() local
[all...] |
| H A D | LiveIntervalUnion.cpp | 159 const LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs() local
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| H A D | MachineRegisterInfo.cpp | 181 VRegInfo[Reg].first = VRegInfo[VReg].first; in cloneVirtualRegister() argument
190 setType(Register VReg,LLT Ty) setType() argument
[all...] |
| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.h | 122 void stackifyVReg(MachineRegisterInfo &MRI, unsigned VReg) { in stackifyVReg()
129 void unstackifyVReg(unsigned VReg) { in unstackifyVReg()
134 bool isVRegStackified(unsigned VReg) const { in isVRegStackified()
142 void setWAReg(unsigned VReg, unsigned WAReg) { in setWAReg()
148 unsigned getWAReg(unsigned VReg) const { in getWAReg()
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| H A D | WebAssemblyReplacePhysRegs.cpp | 84 unsigned VReg = WebAssembly::NoRegister; in runOnMachineFunction() local
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| H A D | WebAssemblyRegNumbering.cpp | 92 Register VReg = Register::index2VirtReg(VRegIdx); runOnMachineFunction() local
[all...] |
| H A D | WebAssemblyRegColoring.cpp | 67 unsigned VReg) { in computeWeight() argument
253 if (MFI.isVRegStackified(VReg)) in runOnMachineFunction() local
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| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.h | 141 storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,Register SrcReg,bool isKill,int FrameIndex,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) storeRegToStackSlot() argument
149 loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,Register DestReg,int FrameIndex,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) loadRegFromStackSlot() argument
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 811 assert(VReg.isVirtual()); in addRegAllocationHint() argument
230 shouldTrackSubRegLiveness(Register VReg) shouldTrackSubRegLiveness() argument
802 setRegAllocationHint(Register VReg,unsigned Type,Register PrefReg) setRegAllocationHint() argument
818 setSimpleHint(Register VReg,Register PrefReg) setSimpleHint() argument
822 clearSimpleHint(Register VReg) clearSimpleHint() argument
831 getRegAllocationHint(Register VReg) getRegAllocationHint() argument
840 getSimpleHint(Register VReg) getSimpleHint() argument
849 getRegAllocationHints(Register VReg) getRegAllocationHints() argument
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| H A D | RegAllocPBQP.h | 148 void setNodeIdForVReg(Register VReg, GraphBase::NodeId NId) { in setNodeIdForVReg()
152 GraphBase::NodeId getNodeIdForVReg(Register VReg) const { in getNodeIdForVReg()
203 void setVReg(Register VReg) { this->VReg = VReg; } in setVReg()
262 Register VReg; variable
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| H A D | FunctionLoweringInfo.h | 108 VReg, enumerator
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| /llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 203 /// If \p VReg i member
185 Register VReg; global() member
[all...] |
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 277 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR() local
327 Register VReg = getVR(Op, VRBaseMap); AddRegisterOperand() local
412 Register VReg = R->getReg(); AddOperand() local
476 ConstrainForSubReg(Register VReg,unsigned SubIdx,MVT VT,bool isDivergent,const DebugLoc & DL) ConstrainForSubReg() argument
638 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); EmitCopyToRegClassNode() local
835 __anonc8a99f720302(unsigned VReg) EmitDbgInstrRef() argument
848 unsigned VReg; EmitDbgInstrRef() local
1225 Register VReg = getVR(GluedNode->getOperand(0), VRBaseMap); EmitMachineNode() local
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| H A D | SDNodeDbgValue.h | 77 static SDDbgOperand fromVReg(unsigned VReg) { in fromVReg()
110 unsigned VReg; ///< Valid for registers. member
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| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 920 Register VReg = MI.getOperand(0).getReg(); getInstrMapping() local
931 Register VReg = MI.getOperand(1).getReg(); getInstrMapping() local
992 Register VReg = MI.getOperand(Idx).getReg(); getInstrMapping() local
1071 Register VReg = MI.getOperand(1).getReg(); getInstrMapping() local
[all...] |
| /llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | RegisterContextDarwin_arm64.h | 75 struct VReg { struct
81 VReg v[32]; argument
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| H A D | RegisterInfoPOSIX_arm64.h | 59 struct VReg { global() struct
65 bytesVReg global() argument
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 295 getIConstantVRegVal(Register VReg,const MachineRegisterInfo & MRI) getIConstantVRegVal() argument
307 getIConstantVRegSExtVal(Register VReg,const MachineRegisterInfo & MRI) getIConstantVRegSExtVal() argument
329 getConstantVRegValWithLookThrough(Register VReg,const MachineRegisterInfo & MRI,bool LookThroughInstrs=true,bool LookThroughAnyExt=false) getConstantVRegValWithLookThrough() argument
427 getIConstantVRegValWithLookThrough(Register VReg,const MachineRegisterInfo & MRI,bool LookThroughInstrs) getIConstantVRegValWithLookThrough() argument
433 getAnyConstantVRegValWithLookThrough(Register VReg,const MachineRegisterInfo & MRI,bool LookThroughInstrs,bool LookThroughAnyExt) getAnyConstantVRegValWithLookThrough() argument
441 getFConstantVRegValWithLookThrough(Register VReg,const MachineRegisterInfo & MRI,bool LookThroughInstrs) getFConstantVRegValWithLookThrough() argument
452 getConstantFPVRegVal(Register VReg,const MachineRegisterInfo & MRI) getConstantFPVRegVal() argument
1329 getAnyConstantSplat(Register VReg,const MachineRegisterInfo & MRI,bool AllowUndef) getAnyConstantSplat() argument
1420 getFConstantSplat(Register VReg,const MachineRegisterInfo & MRI,bool AllowUndef) getFConstantSplat() argument
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| H A D | InstructionSelect.cpp | 262 Register VReg = Register::index2VirtReg(I); runOnMachineFunction() local
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| /llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVGlobalRegistry.cpp | 34 assignIntTypeToVReg(unsigned BitWidth,Register VReg,MachineInstr & I,const SPIRVInstrInfo & TII) assignIntTypeToVReg() argument
43 assignFloatTypeToVReg(unsigned BitWidth,Register VReg,MachineInstr & I,const SPIRVInstrInfo & TII) assignFloatTypeToVReg() argument
52 assignVectTypeToVReg(SPIRVType * BaseType,unsigned NumElements,Register VReg,MachineInstr & I,const SPIRVInstrInfo & TII) assignVectTypeToVReg() argument
61 assignTypeToVReg(const Type * Type,Register VReg,MachineIRBuilder & MIRBuilder,SPIRV::AccessQualifier::AccessQualifier AccessQual,bool EmitIR) assignTypeToVReg() argument
70 assignSPIRVTypeToVReg(SPIRVType * SpirvType,Register VReg,MachineFunction & MF) assignSPIRVTypeToVReg() argument
951 getSPIRVTypeForVReg(Register VReg,const MachineFunction * MF) const getSPIRVTypeForVReg() argument
997 isScalarOfType(Register VReg,unsigned TypeOpcode) const isScalarOfType() argument
1004 isScalarOrVectorOfType(Register VReg,unsigned TypeOpcode) const isScalarOrVectorOfType() argument
[all...] |
| /llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 272 Register VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass); SelectInlineAsmMemoryOperand() local
301 Register VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass); SelectInlineAsmMemoryOperand() local
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| /llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| H A D | NVPTXInstPrinter.cpp | 68 unsigned VReg = Reg.id() & 0x0FFFFFFF; printRegName() local
|