| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMemIntrinsicResults.cpp | 85 unsigned FromReg, unsigned ToReg, in replaceDominatedUses() argument
169 Register ToReg = MI.getOperand(0).getReg(); in optimizeCall() local
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 246 isRevCopyChain(Register FromReg,Register ToReg,int Maxlen) isRevCopyChain() argument
489 Register ToReg = SI.second; removeMapRegEntry() local
781 unsigned ToReg = VirtRegPairs.back(); scanUses() local
[all...] |
| H A D | MachineRegisterInfo.cpp | 391 replaceRegWith(Register FromReg,Register ToReg) replaceRegWith() argument
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| H A D | SplitKit.cpp | 528 buildSingleSubRegCopy(Register FromReg,Register ToReg,MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,unsigned SubIdx,LiveInterval & DestLI,bool Late,SlotIndex Def,const MCInstrDesc & Desc) buildSingleSubRegCopy() argument
546 buildCopy(Register FromReg,Register ToReg,LaneBitmask LaneMask,MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,bool Late,unsigned RegIdx) buildCopy() argument
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| H A D | ModuloSchedule.cpp | 341 replaceRegUsesAfterLoop(unsigned FromReg,unsigned ToReg,MachineBasicBlock * MBB,MachineRegisterInfo & MRI,LiveIntervals & LIS) replaceRegUsesAfterLoop() argument
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| H A D | MachineInstr.cpp | 1274 substituteRegister(Register FromReg,Register ToReg,unsigned SubIdx,const TargetRegisterInfo & RegInfo) substituteRegister() argument
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| /llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 154 unsigned ToReg; global() member
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 3125 replaceAllRegUsesWith(Register FromReg,Register ToReg) replaceAllRegUsesWith() argument
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| H A D | HexagonISelLowering.cpp | 2832 SDValue ToReg = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG); insertVectorPred() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 5726 Register ToReg = UseMI.getOperand(0).getReg(); foldImmediateImpl() local
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 6911 SDValue ToReg = DAG.getCopyToReg(Chain, SL, SGPR01, lowerTrapHsaQueuePtr() local
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