| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRedundantCopyElimination.cpp | 110 Register TargetReg = Cond[1].getReg(); in optimizeBlock() local
|
| /llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 186 emitMask(TargetReg, IndirectBranchMaskReg, STI); in emitInstruction() local
|
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 991 unsigned TargetReg; tracePredStateThroughIndirectBranches() local
1109 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); tracePredStateThroughIndirectBranches() local
1142 Register TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB); tracePredStateThroughIndirectBranches() local
[all...] |
| H A D | X86ExpandPseudo.cpp | 229 auto TargetReg = STI->getTargetTriple().isOSWindows() ? X86::RCX : X86::RDI; expandCALL_RVMARKER() local
|
| H A D | X86ISelLowering.cpp | 59195 Register TargetReg; EmitKCFICheck() local
[all...] |
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 866 Register TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
|
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZAsmPrinter.cpp | 331 Register TargetReg = MI->getOperand(0).getReg(); emitInstruction() local
|
| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 762 Register TargetReg = RealignmentPadding allocateStackSpace() local
852 Register TargetReg = findScratchNonCalleeSaveRegister(&MBB); allocateStackSpace() local
4803 Register TargetReg = MI->getOperand(0).getReg(); inlineStackProbe() local
[all...] |
| H A D | AArch64InstrInfo.cpp | 9532 probedStackAlloc(MachineBasicBlock::iterator MBBI,Register TargetReg,bool FrameSetup) const probedStackAlloc() argument
|
| H A D | AArch64ISelLowering.cpp | 2920 Register TargetReg = MI.getOperand(0).getReg(); EmitDynamicProbedAlloc() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 3063 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo() local
3190 Register TargetReg = MI.getOperand(0).getReg(); expandPostRAPseudo() local
3212 Register TargetReg = MI.getOperand(0).getReg(); expandPostRAPseudo() local
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 179 Register TargetReg) { in buildGitPtr() argument
|
| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3600 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); selectBrJT() local
|
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3312 buildBitFieldInsert(MachineIRBuilder & B,Register TargetReg,Register InsertReg,Register OffsetBits) buildBitFieldInsert() argument
|