Lines Matching defs:TargetReg

800     Register TargetReg = RealignmentPadding
804     emitFrameOffset(MBB, MBBI, DL, TargetReg, AArch64::SP, -AllocSize, &TII,
811           .addReg(TargetReg, RegState::Kill)
890   Register TargetReg = findScratchNonCalleeSaveRegister(&MBB);
891   assert(TargetReg != AArch64::NoRegister);
893   emitFrameOffset(MBB, MBBI, DL, TargetReg, AArch64::SP, -AllocSize, &TII,
898     BuildMI(MBB, MBBI, DL, TII.get(AArch64::ANDXri), TargetReg)
899         .addReg(TargetReg, RegState::Kill)
905       .addReg(TargetReg);
4937 /// Emit a loop to decrement SP until it is equal to TargetReg, with probes at
4939 /// after the loop. The difference between SP and TargetReg must be an exact
4944     Register TargetReg) const {
4968   // CMP SP, TargetReg
4972       .addReg(TargetReg)
5096       Register TargetReg = MI->getOperand(0).getReg();
5097       (void)TII->probedStackAlloc(MI->getIterator(), TargetReg, true);