| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 158 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
162 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
182 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
232 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
238 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
250 unsigned SubIdx = MI.getOperand(2).getImm(); in transferDefinedLanes() local
|
| H A D | ExpandPostRAPseudos.cpp | 69 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
|
| H A D | LiveRangeEdit.cpp | 186 bool Late, unsigned SubIdx, in rematerializeAt() argument
|
| H A D | RegisterCoalescer.cpp | 1817 unsigned SubIdx) { in updateRegDefsUses() argument
2415 const unsigned SubIdx; member in __anonc2b9989c0311::JoinVals
2589 JoinVals(LiveRange & LR,Register Reg,unsigned SubIdx,LaneBitmask LaneMask,SmallVectorImpl<VNInfo * > & newVNInfo,const CoalescerPair & cp,LiveIntervals * lis,const TargetRegisterInfo * TRI,bool SubRangeJoin,bool TrackSubRegLiveness) JoinVals() argument
3110 usesLanes(const MachineInstr & MI,Register Reg,unsigned SubIdx,LaneBitmask Lanes) const usesLanes() argument
[all...] |
| H A D | TwoAddressInstructionPass.cpp | 1863 unsigned SubIdx = mi->getOperand(3).getImm(); runOnMachineFunction() local
1943 unsigned SubIdx = MI.getOperand(i+1).getImm(); eliminateRegSequence() local
|
| H A D | TargetRegisterInfo.cpp | 113 printReg(Register Reg,const TargetRegisterInfo * TRI,unsigned SubIdx,const MachineRegisterInfo * MRI) printReg() argument
|
| H A D | TargetInstrInfo.cpp | 389 unsigned SubIdx, unsigned &Size, in getStackSlotRange() argument
420 Register DestReg, unsigned SubIdx, in reMaterialize() argument
|
| H A D | MachineOperand.cpp | 83 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx, in substVirtReg() argument
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool()
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool()
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
|
| H A D | ARMBaseRegisterInfo.cpp | 498 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
|
| /freebsd-src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | GlobalISelEmitter.cpp | 1286 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(ChildRec); importExplicitUseRenderer() local
1412 auto SubIdx = inferSubRegIndexForNode(Dst->getChild(1)); createAndImportSubInstructionRenderer() local
1457 auto SubIdx = inferSubRegIndexForNode(SubRegChild); createAndImportSubInstructionRenderer() local
1554 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); importExplicitUseRenderers() local
1622 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); importExplicitUseRenderers() local
1853 CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); inferSuperRegisterClass() local
2112 auto SubIdx = inferSubRegIndexForNode(Dst->getChild(1)); runOnPattern() local
2182 auto SubIdx = inferSubRegIndexForNode(SubRegChild); runOnPattern() local
[all...] |
| H A D | CodeGenRegisters.h | |
| H A D | CodeGenRegisters.cpp | |
| H A D | RegisterBankEmitter.cpp | 201 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { visitRegisterBankClasses() local
|
| H A D | CodeGenTarget.cpp | |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TileConfig.cpp | 178 unsigned SubIdx = IsRow ? X86::sub_8bit : X86::sub_16bit; INITIALIZE_PASS_DEPENDENCY() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 24 getMatchingSuperReg(MCRegister Reg,unsigned SubIdx,const MCRegisterClass * RC) const getMatchingSuperReg() argument
|
| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 449 ConstrainForSubReg(Register VReg,unsigned SubIdx,MVT VT,bool isDivergent,const DebugLoc & DL) ConstrainForSubReg() argument
498 unsigned SubIdx = Node->getConstantOperandVal(1); EmitSubregNode() local
554 unsigned SubIdx = N2->getAsZExtVal(); EmitSubregNode() local
653 unsigned SubIdx = Op->getAsZExtVal(); EmitRegSequence() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 211 unsigned SubIdx = X86::NoSubRegister; getSubRegIndex() local
792 unsigned SubIdx; selectTruncOrPtrToInt() local
1252 unsigned SubIdx = X86::NoSubRegister; emitExtractSubreg() local
1290 unsigned SubIdx = X86::NoSubRegister; emitInsertSubreg() local
[all...] |
| H A D | X86LegalizerInfo.cpp | 486 unsigned SubIdx = Query.Opcode == G_EXTRACT ? 0 : 1; X86LegalizerInfo() local
|
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 377 getSubRegIndexName(unsigned SubIdx) getSubRegIndexName() argument
387 getSubRegIndexLaneMask(unsigned SubIdx) getSubRegIndexLaneMask() argument
613 getMatchingSuperReg(MCRegister Reg,unsigned SubIdx,const TargetRegisterClass * RC) getMatchingSuperReg() argument
[all...] |
| H A D | TargetInstrInfo.h | 263 /// register. This also returns the sub-register index in SubIdx. in isCoalescableExtInstr() argument
520 unsigned SubIdx; global() member
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 761 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 744 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); in getIndexInWord32() local
1168 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in extractHvxElementReg() local
1229 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in insertHvxElementReg() local
1385 unsigned SubIdx = (Idx == 0) ? Hexagon::vsub_lo : Hexagon::vsub_hi; in insertHvxSubvectorReg() local
1594 HexagonTargetLowering::extractSubvector(SDValue Vec, MVT SubTy, unsigned SubIdx, in extractSubvector()
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.cpp | 735 getStackSlotRange(const TargetRegisterClass * RC,unsigned SubIdx,unsigned & Size,unsigned & Offset,const MachineFunction & MF) const getStackSlotRange() argument
|