Lines Matching defs:SubIdx

476 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
479   const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
481   // RC is a sub-class of VRC that supports SubIdx.  Try to constrain VReg
486   // VReg has been adjusted.  It can be used with SubIdx operands now.
492   RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
493   assert(RC && "No legal register class for VT supports that SubIdx");
525     unsigned SubIdx = Node->getConstantOperandVal(1);
544         SubIdx == DefSubIdx &&
556       // Reg may not support a SubIdx sub-register, and we may need to
560         Reg = ConstrainForSubReg(Reg, SubIdx,
572         CopyMI.addReg(Reg, 0, SubIdx);
574         CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
581     unsigned SubIdx = N2->getAsZExtVal();
584     // the largest legal register class supporting SubIdx sub-registers.
588     //   %dst = INSERT_SUBREG %src, %sub, SubIdx
593     //   %dst:SubIdx = COPY %sub
599     SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
600     assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
620     MIB.addImm(SubIdx);
680         unsigned SubIdx = Op->getAsZExtVal();
684         TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);