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Searched defs:Stages (Results 1 – 9 of 9) sorted by relevance

/llvm-project/llvm/include/llvm/MCA/
H A DPipeline.h62 SmallVector<std::unique_ptr<Stage>, 8> Stages; variable
/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h239 std::pair<unsigned, bool> Stages = RegToStageDiff[Reg]; in getStagesForReg() local
253 std::pair<unsigned, bool> Stages = RegToStageDiff[Reg]; in getStagesForPhi() local
/llvm-project/llvm/lib/Target/X86/
H A DX86PartialReduction.cpp316 unsigned Stages = Log2_32(NumSplits); trySADReplacement() local
374 unsigned Stages = Log2_32(NumElems); matchAddReduction() local
H A DX86ISelLowering.cpp44480 unsigned Stages = Log2_32(VT.getVectorNumElements()); combineVPDPBUSDPattern() local
44555 unsigned Stages = Log2_32(VT.getVectorNumElements()); combineBasicSADPattern() local
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/llvm-project/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h89 const InstrStage *Stages; // Instruction itinerary stages global() variable
H A DMCInstrItineraries.h114 const InstrStage *Stages = nullptr; ///< Array of stages selected variable
/llvm-project/llvm/lib/CodeGen/
H A DWindowScheduler.cpp621 DenseMap<MachineInstr *, int> Cycles, Stages; expand() local
H A DMachinePipeliner.cpp695 DenseMap<MachineInstr *, int> Cycles, Stages; schedule() local
1076 computeScheduledInsts(const SwingSchedulerDAG * SSD,SMSchedule & Schedule,std::vector<MachineInstr * > & OrderedInsts,DenseMap<MachineInstr *,unsigned> & Stages) computeScheduledInsts() argument
1435 computeMaxSetPressure(const OrderedInstsTy & OrderedInsts,Instr2StageTy & Stages,const unsigned StageCount) const computeMaxSetPressure() argument
1549 Instr2StageTy Stages; detect() local
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/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp12253 unsigned Stages = Log2_32(Op.getValueType().getVectorNumElements()); matchBinOpReduction() local