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Searched defs:Stage (Results 1 – 19 of 19) sorted by relevance

/freebsd-src/contrib/llvm-project/llvm/lib/ObjectYAML/
H A DDXContainerYAML.cpp53 uint16_t Stage) in PSVInfo() argument
143 Triple::EnvironmentType Stage = dxbc::getShaderStage(PSV.Info.ShaderStage); mapping() local
268 Triple::EnvironmentType Stage = dxbc::getShaderStage(Info.ShaderStage); mapInfoForVersion() local
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h94 DenseMap<MachineInstr *, int> Stage; variable
110 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocGreedy.h68 LiveRangeStage Stage = RS_New; member
90 void setStage(Register Reg, LiveRangeStage Stage) { in setStage() argument
95 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
H A DModuloSchedule.cpp1612 int Stage = getStage(MI); filterInstructions() local
1637 moveStageBetweenBlocks(MachineBasicBlock * DestBB,MachineBasicBlock * SourceBB,unsigned Stage) moveStageBetweenBlocks() argument
1791 unsigned Stage = Schedule.getNumStages() - 1 + I - J; peelPrologAndEpilogs() local
1924 int Stage = getStage(MI); rewriteUsesOf() local
2152 parseSymbolString(StringRef S,int & Cycle,int & Stage) parseSymbolString() argument
2176 DenseMap<MachineInstr *, int> Cycle, Stage; runOnLoop() local
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H A DMLRegAllocPriorityAdvisor.cpp297 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); getPriorityImpl() local
H A DRegAllocGreedy.cpp292 Stage = RS_Assign; in enqueue() local
309 if (Stage == RS_Split) { in getPriority() local
2439 LiveRangeStage Stage = ExtraInfo->getStage(VirtReg); selectOrSplitImpl() local
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H A DMachinePipeliner.cpp1032 for (int Stage = 0, LastStage = Schedule.getMaxStageCount(); computeScheduledInsts() local
1436 const auto Stage = Stages[MI]; computeMaxSetPressure() local
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/freebsd-src/contrib/llvm-project/llvm/lib/DWARFLinker/Parallel/
H A DDWARFLinkerCompileUnit.h56 enum class Stage : uint8_t { enum
101 void setStage(Stage Stage) { this->Stage = Stage; } in setStage() argument
717 std::atomic<Stage> Stage; variable
/freebsd-src/contrib/llvm-project/llvm/utils/TableGen/
H A DDFAPacketizerEmitter.cpp277 for (NfaStateTy Stage : InsnClass) { in emitForItineraries() local
H A DSubtargetEmitter.cpp353 const Record *Stage = StageList[i]; FormItineraryStageString() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp442 unsigned Stage = II[SchedClass].LastStage - 1; in getCVIResources() local
471 for (unsigned Stage = II[SchedClass].FirstStage + 1; in getOtherReservedSlots() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.cpp647 auto Stage = createSchedStage(S.getCurrentStage()); runSchedStages() local
/freebsd-src/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DDXContainer.h243 swapBytes(Triple::EnvironmentType Stage) swapBytes() argument
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h612 enum InstrStage Stage; variable
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2814 for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) { SelectMVE_VLD() local
H A DARMBaseInstrInfo.cpp6884 for (int Stage = 0, StageEnd = SMS.getMaxStageCount(); Stage <= StageEnd; tooMuchRegisterPressure() local
/freebsd-src/contrib/llvm-project/clang/lib/Sema/
H A DSemaDecl.cpp12614 DiagnoseHLSLAttrStageMismatch(const Attr * A,HLSLShaderAttr::ShaderType Stage,std::initializer_list<HLSLShaderAttr::ShaderType> AllowedStages) DiagnoseHLSLAttrStageMismatch() argument
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp16257 for (unsigned Stage = 0; Stage != 6; ++Stage) { computeGREVOrGORC() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp5039 for (unsigned Stage = 0; Stage != Repetitions; ++Stage) { createPackShuffleMask() local
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