| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CSEMIRBuilder.cpp | 109 profileEverything(unsigned Opc,ArrayRef<DstOp> DstOps,ArrayRef<SrcOp> SrcOps,std::optional<unsigned> Flags,GISelInstProfileBuilder & B) const profileEverything() argument
172 buildInstr(unsigned Opc,ArrayRef<DstOp> DstOps,ArrayRef<SrcOp> SrcOps,std::optional<unsigned> Flag) buildInstr() argument
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| H A D | MachineIRBuilder.cpp | 1118 buildInstr(unsigned Opc,ArrayRef<DstOp> DstOps,ArrayRef<SrcOp> SrcOps,std::optional<unsigned> Flags) buildInstr() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 72 SmallVector<SrcOp, 2> SrcOps; ///< Source registers. global() member
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| H A D | AArch64InstructionSelector.cpp | 4404 emitInstr(unsigned Opcode,std::initializer_list<llvm::DstOp> DstOps,std::initializer_list<llvm::SrcOp> SrcOps,MachineIRBuilder & MIRBuilder,const ComplexRendererFns & RenderFns) const emitInstr() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 4160 SmallVector<SDValue> SrcOps(Ops.begin(), Ops.end()); getAVX512Node() local
22044 matchScalarReduction(SDValue Op,ISD::NodeType BinOp,SmallVectorImpl<SDValue> & SrcOps,SmallVectorImpl<APInt> * SrcMask=nullptr) matchScalarReduction() argument
38949 combineX86ShufflesRecursively(ArrayRef<SDValue> SrcOps,int SrcOpIndex,SDValue Root,ArrayRef<int> RootMask,ArrayRef<const SDNode * > SrcNodes,unsigned Depth,unsigned MaxDepth,bool HasVariableMask,bool AllowVariableCrossLaneMask,bool AllowVariablePerLaneMask,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86ShufflesRecursively() argument
48576 SmallVector<SDValue, 2> SrcOps; combineAnd() local
49371 SmallVector<SDValue, 2> SrcOps; combineOr() local
50728 SmallVector<SDValue, 2> SrcOps; isHorizontalBinOp() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 23672 SmallVector<SDValue, 4> SrcOps; combineConcatVectorOfCasts() local
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