| /llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCDuplexInfo.cpp | 190 MCRegister DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
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| H A D | HexagonMCCompound.cpp | 81 MCRegister DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
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| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZPostRewrite.cpp | 104 Register Src1Reg = MBBI->getOperand(1).getReg(); in selectSELRMux() local
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| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 692 Register Src1Reg = MI.getOperand(1).getReg(); matchDupLane() local
748 Register Src1Reg = MI.getOperand(1).getReg(); applyDupLane() local
769 Register Src1Reg = Unmerge.getReg(Unmerge.getNumOperands() - 1); matchScalarizeVectorUnmerge() local
780 Register Src1Reg = Unmerge.getReg(Unmerge.getNumOperands() - 1); applyScalarizeVectorUnmerge() local
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| H A D | AArch64InstructionSelector.cpp | 1891 Register Src1Reg = I.getOperand(1).getReg(); selectVectorSHL() local
1937 Register Src1Reg = I.getOperand(1).getReg(); selectVectorAshrLshr() local
3738 Register Src1Reg = I.getOperand(1).getReg(); selectMergeValues() local
5002 Register Src1Reg = I.getOperand(1).getReg(); selectShuffleVector() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 275 Register Src1Reg = MI->getOperand(2).getReg(); in ExpandFPMLxInstruction() local
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| /llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 623 Register Src1Reg = Concat.getSourceReg(0); findValueFromConcat() local
655 Register Src1Reg = BV.getSourceReg(0); findValueFromBuildVector() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1288 Register Src1Reg = MI.getOperand(1).getReg(); expandPostRAPseudo() local
1312 Register Src1Reg = MI.getOperand(1).getReg(); expandPostRAPseudo() local
3427 Register DstReg, SrcReg, Src1Reg, Src2Reg; getCompoundCandidateGroup() local
3925 Register DstReg, SrcReg, Src1Reg, Src2Reg; getDuplexCandidateGroup() local
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| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1038 Register Src1Reg = getRegForValue(SI->getTrueValue()); selectSelect() local
1933 Register Src1Reg = getRegForValue(I->getOperand(1)); selectDivRem() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 2652 Register Src1Reg = getRegForValue(Src1Val); optimizeSelect() local
2775 Register Src1Reg = getRegForValue(SI->getTrueValue()); selectSelect() local
4635 Register Src1Reg = getRegForValue(I->getOperand(1)); selectRem() local
4707 Register Src1Reg = getRegForValue(I->getOperand(1)); selectMul() local
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 437 Register Src1Reg = I.getOperand(3).getReg(); selectG_UADDO_USUBO_UADDE_USUBE() local
791 Register Src1Reg = I.getOperand(2).getReg(); selectG_INSERT() local
1027 Register Src1Reg = I.getOperand(3).getReg(); selectG_INTRINSIC() local
1381 Register Src1Reg = selectIntrinsicCmp() local
[all...] |
| H A D | AMDGPURegisterBankInfo.cpp | 4611 Register Src1Reg = MI.getOperand(3).getReg(); getInstrMapping() local
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| H A D | AMDGPULegalizerInfo.cpp | 2481 Register Src1Reg = MI.getOperand(2).getReg(); legalizeFrem() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 4674 Register Src1Reg = PtrAdd.getBaseReg(); reassociationCanBreakAddressingModePattern() local
4739 Register Src1Reg = MI.getOperand(1).getReg(); matchReassocConstantInnerRHS() local
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 18197 Register Src1Reg = MI.getOperand(1).getReg(); emitQuietFCMP() local
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