| /llvm-project/clang/test/FixIt/ |
| H A D | fixit.cpp | 288 struct Shr { struct
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| /llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 636 if (Instruction *Shr = dyn_cast<Instruction>(I->getOperand(0))) SimplifyDemandedUseBits() local
1323 simplifyShrShlDemandedBits(Instruction * Shr,const APInt & ShrOp1,Instruction * Shl,const APInt & ShlOp1,const APInt & DemandedMask,KnownBits & Known) simplifyShrShlDemandedBits() argument
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| H A D | InstCombineShifts.cpp | 1116 BinaryOperator *Shr; visitShl() local
1157 Value *Shr = Op0BO->getOperand(0); visitShl() local
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| H A D | InstCombineMulDivRem.cpp | 1689 Value *Shr = Builder.CreateLShr(Op0, CNegLog2, I.getName(), I.isExact()); visitSDiv() local
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| H A D | InstCombineCompares.cpp | 2456 foldICmpShrConstant(ICmpInst & Cmp,BinaryOperator * Shr,const APInt & C) foldICmpShrConstant() argument
[all...] |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | ExpandLargeFpConvert.cpp | 369 Value *Shr = expandIToFP() local
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| /llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyIndVar.cpp | 836 BinaryOperator *Shr = cast<BinaryOperator>(U); strengthenRightShift() local
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| /llvm-project/clang/lib/AST/Interp/ |
| H A D | Interp.h | |
| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 2437 auto *Shr = dyn_cast_or_null<Instruction>(Add->getUniqueUndroppableUser()); isExtPartOfAvgExpr() local
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| H A D | AArch64ISelLowering.cpp | 19224 __anonb71a9e6e2c02(SDValue Shr) performConcatVectorsCombine() argument
19264 SDValue Shr = performConcatVectorsCombine() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1995 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); widenScalarUnmergeValues() local
7637 auto Shr = MIRBuilder.buildLShr(SrcIntTy, SrcReg, ShiftAmt); lowerExtract() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 2750 SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Op0, ShiftConst); ExpandLegalINT_TO_FP() local
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| H A D | DAGCombiner.cpp | 27653 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt); SimplifySelectCC() local
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2438 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); LowerFTRUNC() local
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| H A D | AMDGPULegalizerInfo.cpp | 2541 auto Shr = B.buildAShr(S64, FractMask, Exp); legalizeIntrinsicTrunc() local
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