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Searched defs:ShiftAmt (Results 1 – 25 of 64) sorted by relevance

123

/llvm-project/llvm/lib/Analysis/
H A DDemandedBits.cpp178 AB = AOut.lshr(ShiftAmt); in determineLiveOperandBits() local
130 uint64_t ShiftAmt = SA->urem(BitWidth); determineLiveOperandBits() local
195 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1); determineLiveOperandBits() local
209 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1); determineLiveOperandBits() local
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H A DConstantFolding.cpp218 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1); FoldBitCast() local
272 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1); FoldBitCast() local
/llvm-project/llvm/include/llvm/ADT/
H A DAPInt.h807 ashr(unsigned ShiftAmt) ashr() argument
814 ashrInPlace(unsigned ShiftAmt) ashrInPlace() argument
838 lshrInPlace(unsigned ShiftAmt) lshrInPlace() argument
888 ashr(const APInt & ShiftAmt) ashr() argument
900 lshr(const APInt & ShiftAmt) lshr() argument
912 shl(const APInt & ShiftAmt) shl() argument
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/llvm-project/llvm/lib/Support/
H A DKnownBits.cpp288 auto ShiftByConst = [&](const KnownBits &LHS, unsigned ShiftAmt) { in shl() argument
353 for (unsigned ShiftAmt = MinShiftAmount; ShiftAmt <= MaxShiftAmount; in shl() local
373 __anon8264ec8e0502(const KnownBits &LHS, unsigned ShiftAmt) lshr() argument
411 for (unsigned ShiftAmt = MinShiftAmount; ShiftAmt <= MaxShiftAmount; lshr() local
431 __anon8264ec8e0602(const KnownBits &LHS, unsigned ShiftAmt) ashr() argument
471 for (unsigned ShiftAmt = MinShiftAmount; ShiftAmt <= MaxShiftAmount; ashr() local
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H A DAPInt.cpp1026 ashrSlowCase(unsigned ShiftAmt) ashrSlowCase() argument
1075 lshrSlowCase(unsigned ShiftAmt) lshrSlowCase() argument
1087 shlSlowCase(unsigned ShiftAmt) shlSlowCase() argument
2236 unsigned ShiftAmt = (Radix == 16 ? 4 : (Radix == 8 ? 3 : 1)); toString() local
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/llvm-project/llvm/lib/Transforms/Utils/
H A DVNCoercion.cpp140 uint64_t ShiftAmt = DL.getTypeStoreSizeInBits(StoredValTy).getFixedValue() - coerceAvailableValueToLoadType() local
320 unsigned ShiftAmt; getStoreValueForLoadHelper() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ConditionOptimizer.cpp175 unsigned ShiftAmt = AArch64_AM::getShiftValue(I.getOperand(3).getImm()); in findSuitableCompare() local
H A DAArch64ExpandImm.cpp69 unsigned ShiftAmt = 0; in tryToreplicateChunks() local
H A DAArch64ISelDAGToDAG.cpp600 unsigned ShiftAmt; SelectArithImmed() local
2763 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); getUsefulBitsFromOrWithShiftedReg() local
2771 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); getUsefulBitsFromOrWithShiftedReg() local
3668 SDValue ShiftAmt = N->getOperand(1); tryShiftAmountMod() local
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/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp658 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth - 1); SimplifyDemandedUseBits() local
721 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); SimplifyDemandedUseBits() local
805 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1); SimplifyDemandedUseBits() local
1037 uint64_t ShiftAmt = SA->urem(BitWidth); SimplifyDemandedUseBits() local
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H A DInstCombineCasts.cpp1080 uint64_t ShiftAmt = Amt->getZExtValue(); canEvaluateZExtd() local
1338 unsigned ShiftAmt = KnownZeroMask.countr_zero(); transformSExtICmp() local
1352 unsigned ShiftAmt = KnownZeroMask.countl_zero(); transformSExtICmp() local
/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp469 unsigned &ShiftAmt, unsigned &AddOpc) { in generateTwoRegInstSeq() argument
/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp280 auto ShiftAmt = in buildLCMMergePieces() local
1864 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); widenScalarMergeValues() local
1994 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); widenScalarUnmergeValues() local
2522 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); widenScalar() local
3516 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); lowerLoad() local
3616 auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, LargeSplitSize); lowerStore() local
3771 auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1); lower() local
5281 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1); narrowScalarShift() local
7210 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); lowerFCopySign() local
7215 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size); lowerFCopySign() local
7354 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); lowerMergeValues() local
7395 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset); lowerUnmergeValues() local
7636 auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset); lowerExtract() local
7721 auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset); lowerInsert() local
7956 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt); lowerBswap() local
7966 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i); lowerBswap() local
8087 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, SizeInBits); lowerSMULH_UMULH() local
8351 auto ShiftAmt = lowerAbsToAddXor() local
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H A DLoadStoreOpt.cpp664 m_any_of(m_GLShr(m_Reg(FoundSrcVal), m_ICst(ShiftAmt)), in getTruncStoreByteOffset() local
H A DCombinerHelper.cpp2064 int64_t ShiftAmt = MaybeShiftAmtVal->getSExtValue(); matchCombineShlOfExtend() local
2079 auto ShiftAmt = Builder.buildConstant(ExtSrcTy, ShiftAmtVal); applyCombineShlOfExtend() local
2183 unsigned ShiftAmt = Dst0Ty.getSizeInBits(); matchCombineUnmergeConstant() local
2400 unsigned ShiftAmt; tryCombineShiftToUnmerge() local
2705 Register ShiftAmt = ShiftMI->getOperand(2).getReg(); applyCombineTruncOfShift() local
3248 int64_t ShiftAmt; applyAshShlToSextInreg() local
5535 auto ShiftAmt = applyUMulHToLShr() local
6280 std::optional<ValueAndVReg> ShiftAmt; matchTruncLshrBuildVectorFold() local
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/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2291 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8); in foldMaskedShiftToBEXTR() local
2120 unsigned ShiftAmt = Shift.getConstantOperandVal(1); foldMaskedShiftToScaledMask() local
2193 unsigned ShiftAmt = Shift.getConstantOperandVal(1); foldMaskAndShiftToScale() local
2366 uint64_t ShiftAmt = N.getConstantOperandVal(1); matchIndexRecursively() local
3880 __anonb5bafcbc1002(SDValue ShiftAmt, unsigned Bitwidth) matchBitExtract() argument
4051 SDValue ShiftAmt = X.getOperand(1); matchBitExtract() local
4291 SDValue ShiftAmt = OrigShiftAmt; tryShiftAmountMod() local
6036 unsigned ShiftAmt; Select() local
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H A DX86InstCombineIntrinsic.cpp288 auto ShiftAmt = ConstantInt::get(SVT, Count.zextOrTrunc(BitWidth)); simplifyX86immShift() local
2223 Value *ShiftAmt = ConstantInt::get(II.getType(), MaskIdx); instCombineIntrinsic() local
2266 Value *ShiftAmt = ConstantInt::get(II.getType(), MaskIdx); instCombineIntrinsic() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp325 int64_t ShiftAmt; in matchCvtF32UByteN() local
H A DR600ISelLowering.cpp1065 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, lowerPrivateTruncStore() local
1294 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, lowerPrivateExtLoad() local
H A DAMDGPUISelDAGToDAG.cpp70 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) { isExtractHiElt() local
3434 ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); SelectSWMMACIndex8() local
3453 ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); SelectSWMMACIndex16() local
/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp580 unsigned ShiftAmt, AddOpc; shouldBeInConstantPool() local
/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1921 insertMultibyteShift(MachineInstr & MI,MachineBasicBlock * BB,MutableArrayRef<std::pair<Register,int>> Regs,ISD::NodeType Opc,int64_t ShiftAmt) insertMultibyteShift() argument
2193 int64_t ShiftAmt = MI.getOperand(4).getImm(); insertWideShift() local
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/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp185 unsigned ShiftAmt, AddSubOpc; in matchAArch64MulConstCombine() local
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp221 unsigned ShiftAmt, AddOpc; in selectImm() local
2528 uint64_t ShiftAmt = 0; SelectAddrRegRegScale() local
2889 __anoncaf6453e0402(SDValue N, unsigned ShiftAmt) selectSExtBits() argument
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/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp1575 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize * (Ratio - 1); in executeBitCastInst() local
1591 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize * (Ratio - 1); in executeBitCastInst() local

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