| /llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterScavenging.cpp | 422 N->addRegisterKilled(SReg, &TRI, false); in scavengeFrameVirtualRegsInBlock() local
448 I->addRegisterDead(SReg, &TRI, false); in scavengeFrameVirtualRegsInBlock() local
382 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), scavengeVReg() local
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| H A D | LivePhysRegs.cpp | 268 if (any_of(TRI.superregs(Reg), [&](MCPhysReg SReg) { in addLiveIns() argument
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| H A D | PrologEpilogInserter.cpp | 1294 for (MCPhysReg SReg : TRI.sub_and_superregs_inclusive(Reg)) insertZeroCallUsedRegs() local
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| H A D | BranchFolding.cpp | 864 if (any_of(TRI->superregs(Reg), [&](MCPhysReg SReg) { in mergeCommonTails() argument
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | VirtRegMap.h | 153 setIsSplitFromReg(Register virtReg,Register SReg) setIsSplitFromReg() argument
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR() argument
153 getPrefSPRLane(unsigned SReg) getPrefSPRLane() argument
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 5076 getCorrespondingDRegAndLane(const TargetRegisterInfo * TRI,unsigned SReg,unsigned & Lane) getCorrespondingDRegAndLane() argument
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreEmitPeephole.cpp | 128 Register SReg; optimizeVccBranch() local
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| H A D | SIShrinkInstructions.cpp | 981 Register SReg = Src2->getReg(); runOnMachineFunction() local
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| H A D | SIInstrInfo.cpp | 1283 .addReg(SReg); in insertVectorSelect() local
1240 Register SReg = MRI.createVirtualRegister(BoolXExecRC); insertVectorSelect() local
1253 Register SReg = MRI.createVirtualRegister(BoolXExecRC); insertVectorSelect() local
1267 Register SReg = MRI.createVirtualRegister(BoolXExecRC); insertVectorSelect() local
1297 Register SReg = MRI.createVirtualRegister(BoolXExecRC); insertVectorSelect() local
1309 Register SReg = MRI.createVirtualRegister(BoolXExecRC); insertVectorSelect() local
1327 Register SReg = MRI.createVirtualRegister(BoolXExecRC); insertVectorSelect() local
[all...] |
| H A D | SIISelLowering.cpp | 15681 Register SReg = ST.isWave32() finalizeLowering() local
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| /llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | MemRegion.h | 1040 ParamVarRegion(const Expr *OE, unsigned Idx, const MemRegion *SReg) in ParamVarRegion() argument
1317 const SubRegion *SReg) in CXXBaseObjectRegion() argument
1355 CXXDerivedObjectRegion(const CXXRecordDecl *DerivedD, const SubRegion *SReg) in CXXDerivedObjectRegion() argument
[all...] |
| /llvm-project/clang/lib/StaticAnalyzer/Core/ |
| H A D | MemRegion.cpp | 320 ProfileRegion(llvm::FoldingSetNodeID & ID,const Expr * OE,unsigned Idx,const MemRegion * SReg) ProfileRegion() argument
422 ProfileRegion(llvm::FoldingSetNodeID & ID,const CXXRecordDecl * RD,bool IsVirtual,const MemRegion * SReg) ProfileRegion() argument
434 ProfileRegion(llvm::FoldingSetNodeID & ID,const CXXRecordDecl * RD,const MemRegion * SReg) ProfileRegion() argument
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| /llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.cpp | 369 Register SReg = ExpandMOVI() local
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| /llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4931 unsigned SReg = Inst.getOperand(1).getReg(); expandRotation() local
4994 unsigned SReg = Inst.getOperand(1).getReg(); expandRotationImm() local
5056 unsigned SReg = Inst.getOperand(1).getReg(); expandDRotation() local
5119 unsigned SReg = Inst.getOperand(1).getReg(); expandDRotationImm() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 1737 Register SRegHi, SReg, VSReg; eliminateFrameIndex() local
[all...] |
| H A D | PPCISelLowering.cpp | 12371 Register SReg = RegInfo.createVirtualRegister(GPRC); EmitPartwordAtomicBinary() local
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