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Searched defs:SOffset (Results 1 – 12 of 12) sorted by relevance

/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp1315 SelectMUBUF(SDValue Addr,SDValue & Ptr,SDValue & VAddr,SDValue & SOffset,SDValue & Offset,SDValue & Offen,SDValue & Idxen,SDValue & Addr64) const SelectMUBUF() argument
1403 SelectMUBUFAddr64(SDValue Addr,SDValue & SRsrc,SDValue & VAddr,SDValue & SOffset,SDValue & Offset) const SelectMUBUFAddr64() argument
1445 SelectMUBUFScratchOffen(SDNode * Parent,SDValue Addr,SDValue & Rsrc,SDValue & VAddr,SDValue & SOffset,SDValue & ImmOffset) const SelectMUBUFScratchOffen() argument
1524 SelectMUBUFScratchOffset(SDNode * Parent,SDValue Addr,SDValue & SRsrc,SDValue & SOffset,SDValue & Offset) const SelectMUBUFScratchOffset() argument
1566 SelectMUBUFOffset(SDValue Addr,SDValue & SRsrc,SDValue & SOffset,SDValue & Offset) const SelectMUBUFOffset() argument
1987 SelectSMRDOffset(SDValue ByteOffsetNode,SDValue * SOffset,SDValue * Offset,bool Imm32Only,bool IsBuffer) const SelectSMRDOffset() argument
2074 SelectSMRDBaseOffset(SDValue Addr,SDValue & SBase,SDValue * SOffset,SDValue * Offset,bool Imm32Only,bool IsBuffer) const SelectSMRDBaseOffset() argument
2112 SelectSMRD(SDValue Addr,SDValue & SBase,SDValue * SOffset,SDValue * Offset,bool Imm32Only) const SelectSMRD() argument
2146 SelectSMRDSgprImm(SDValue Addr,SDValue & SBase,SDValue & SOffset,SDValue & Offset) const SelectSMRDSgprImm() argument
2163 SelectSMRDBufferSgprImm(SDValue N,SDValue & SOffset,SDValue & Offset) const SelectSMRDBufferSgprImm() argument
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H A DAMDGPUInstructionSelector.cpp4223 selectSmrdOffset(MachineOperand & Root,Register & Base,Register * SOffset,int64_t * Offset) const selectSmrdOffset() argument
4322 Register Base, SOffset; selectSmrdSgpr() local
4332 Register Base, SOffset; selectSmrdSgprImm() local
5151 splitIllegalMUBUFOffset(MachineIRBuilder & B,Register & SOffset,int64_t & ImmOffset) const splitIllegalMUBUFOffset() argument
5165 selectMUBUFAddr64Impl(MachineOperand & Root,Register & VAddr,Register & RSrcReg,Register & SOffset,int64_t & Offset) const selectMUBUFAddr64Impl() argument
5215 selectMUBUFOffsetImpl(MachineOperand & Root,Register & RSrcReg,Register & SOffset,int64_t & Offset) const selectMUBUFOffsetImpl() argument
5243 Register SOffset; selectMUBUFAddr64() local
5278 Register SOffset; selectMUBUFOffset() local
5306 Register SOffset = Root.getReg(); selectBUFSOffset() local
5358 Register SOffset; selectSMRDBufferSgprImm() local
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H A DSIRegisterInfo.cpp906 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); resolveFrameIndex() local
1338 MCRegister SOffset = ScratchOffsetReg; buildSpillLoadStore() local
2560 auto &SOffset = *TII->getNamedOperand(*MI, AMDGPU::OpName::soffset); eliminateFrameIndex() local
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H A DSIISelLowering.cpp8329 selectSOffset(SDValue SOffset,SelectionDAG & DAG,const GCNSubtarget * Subtarget) selectSOffset() argument
8344 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); lowerRawBufferAtomicIntrin() local
8378 auto SOffset = selectSOffset(Op.getOperand(6), DAG, Subtarget); lowerStructBufferAtomicIntrin() local
8541 auto SOffset = selectSOffset(Op.getOperand(4), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
8566 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
8584 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
8615 auto SOffset = selectSOffset(Op.getOperand(4), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
8642 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
8874 auto SOffset = selectSOffset(Op.getOperand(6), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
8897 auto SOffset = selectSOffset(Op.getOperand(7), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
9349 auto SOffset = selectSOffset(Op.getOperand(6), DAG, Subtarget); LowerINTRINSIC_VOID() local
9377 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); LowerINTRINSIC_VOID() local
9458 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); LowerINTRINSIC_VOID() local
9509 auto SOffset = selectSOffset(Op.getOperand(6), DAG, Subtarget); LowerINTRINSIC_VOID() local
9848 uint32_t SOffset, ImmOffset; setBufferOffsets() local
9859 uint32_t SOffset, ImmOffset; setBufferOffsets() local
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H A DAMDGPURegisterBankInfo.cpp1255 if (TII->splitMUBUFOffset(*Imm, SOffset, ImmOffset, Alignment)) { in setBufferOffsets() local
1273 uint32_t SOffset, ImmOffset; setBufferOffsets() local
1363 Register SOffset; applyMappingSBufferLoad() local
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H A DAMDGPULegalizerInfo.cpp5635 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); legalizeBufferStore() local
5688 buildBufferLoad(unsigned Opc,Register LoadDstReg,Register RSrc,Register VIndex,Register VOffset,Register SOffset,unsigned ImmOffset,unsigned Format,unsigned AuxiliaryData,MachineMemOperand * MMO,bool IsTyped,bool HasVIndex,MachineIRBuilder & B) buildBufferLoad() argument
5746 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); legalizeBufferLoad() local
5979 Register SOffset = MI.getOperand(5 + OpOffset).getReg(); legalizeBufferAtomic() local
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H A DSILoadStoreOptimizer.cpp97 bool SOffset = false; member
H A DSIInstrInfo.cpp446 const MachineOperand *SOffset = getMemOperandsWithOffsetWidth() local
6738 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); legalizeOperands() local
8924 splitMUBUFOffset(uint32_t Imm,uint32_t & SOffset,uint32_t & ImmOffset,Align Alignment) const splitMUBUFOffset() argument
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H A DGCNHazardRecognizer.cpp830 const MachineOperand *SOffset = createsVALUHazard() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp722 unsigned SOffset = 0; in getMachineOpValue() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp332 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp5617 isAArch64FrameOffsetLegal(const MachineInstr & MI,StackOffset & SOffset,bool * OutUseUnscaledOp,unsigned * OutUnscaledOp,int64_t * EmittableOffset) isAArch64FrameOffsetLegal() argument