| /llvm-project/clang/test/Sema/ |
| H A D | builtins-hexagon-v55.c | 7 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60()
14 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62()
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| H A D | builtins-hexagon-v62.c | 7 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60()
14 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62()
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| H A D | builtins-hexagon-v65.c | 5 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60()
9 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62()
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| H A D | builtins-hexagon-v60.c | 7 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60()
14 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62()
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| /llvm-project/clang-tools-extra/clangd/unittests/ |
| H A D | Annotations.cpp | 69 std::vector<clangd::Range> Rs; in ranges() local
81 std::vector<std::pair<clangd::Range, llvm::StringRef>> Rs; in rangesWithPayload() local
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| /llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_mips.cpp | 40 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction() argument
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
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| H A D | xray_mips64.cpp | 41 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction() argument
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
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| /llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 578 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodeDAHIDATIMMR6() local
592 InsnType Rs = fieldFromInstruction(insn, 21, 5); DecodeDAHIDATI() local
617 InsnType Rs = fieldFromInstruction(insn, 21, 5); DecodeAddiGroupBranch() local
647 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodePOP35GroupBranchMMR6() local
690 InsnType Rs = fieldFromInstruction(insn, 21, 5); DecodeDaddiGroupBranch() local
720 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodePOP37GroupBranchMMR6() local
761 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodePOP65GroupBranchMMR6() local
800 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodePOP75GroupBranchMMR6() local
842 InsnType Rs = fieldFromInstruction(insn, 21, 5); DecodeBlezlGroupBranch() local
887 InsnType Rs = fieldFromInstruction(insn, 21, 5); DecodeBgtzlGroupBranch() local
929 InsnType Rs = fieldFromInstruction(insn, 21, 5); DecodeBgtzGroupBranch() local
978 InsnType Rs = fieldFromInstruction(insn, 21, 5); DecodeBlezGroupBranch() local
1034 InsnType Rs = fieldFromInstruction(Insn, 21, 5); DecodeDEXT() local
1076 InsnType Rs = fieldFromInstruction(Insn, 21, 5); DecodeDINS() local
1094 InsnType Rs = fieldFromInstruction(Insn, 21, 5); DecodeCRC() local
2441 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodeBgtzGroupBranchMMR6() local
2490 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodeBlezGroupBranchMMR6() local
[all...] |
| /llvm-project/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 154 switch (Rs) { in DecodeSrcAddrMode() argument
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); DecodeSrcAddrModeI() local
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); DecodeSrcAddrModeII() local
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| /llvm-project/llvm/unittests/Remarks/ |
| H A D | YAMLRemarksSerializerTest.cpp | 26 remarks::SerializerMode Mode, ArrayRef<remarks::Remark> Rs, in check()
284 SmallVector<remarks::Remark, 2> Rs; in TEST() local
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| /llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 28 struct Rs { struct
46 Rs rs1; \ argument
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| H A D | RISCVCInstructions.h | 26 operator Rs() { return Rs{rd + (shift ? 8 : 0)}; } in Rs() function
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| /llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1684 MCOperand &Rs = Inst.getOperand(2); processInstruction() local
1704 MCOperand &Rs = Inst.getOperand(2); processInstruction() local
1724 MCOperand &Rs = Inst.getOperand(2); processInstruction() local
1747 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1780 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1790 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1832 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1849 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1978 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
[all...] |
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 147 const USet &Rs = I.second; in isInduction() local
373 Register Rs = MI->getOperand(1).getReg(); in profit() local
475 USet &Rs) { in collectIndRegsForLoop() argument
579 USet Rs; collectIndRegs() local
[all...] |
| H A D | HexagonConstExtenders.cpp | 293 Register Rs; member
447 HCE::Register Rs; global() member
1504 Register Rs = ExtI.second.Rs; // Only one reg allowed now. calculatePlacement() local
1801 Register Rs = MI.getOperand(IsSub ? 3 : 2); replaceInstrExpr() local
[all...] |
| H A D | HexagonAsmPrinter.cpp | 412 MCOperand &Rs = Inst.getOperand(1); HexagonProcessInstruction() local
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| H A D | HexagonBitTracker.cpp | 295 __anon356067470702(const BT::RegisterCell &Rs, const BT::RegisterCell &Rt, uint16_t BW, bool Odd) evaluate() argument
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| H A D | HexagonBitSimplify.cpp | 1919 matchPackhl(unsigned SelfR,const BitTracker::RegisterCell & RC,BitTracker::RegisterRef & Rs,BitTracker::RegisterRef & Rt) matchPackhl() argument
2054 BitTracker::RegisterRef Rs, Rt; genPackhl() local
[all...] |
| /llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolutionDivision.cpp | 151 SmallVector<const SCEV *, 2> Qs, Rs; in visitAddExpr() local
|
| /llvm-project/clang-tools-extra/test/clang-tidy/checkers/modernize/ |
| H A D | raw-string-literal.cpp | 39 char const *const Rs("goink\\\036"); variable
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| /llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 201 MCOperand Rs, Rt; in getCompoundInsn() local
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVMergeBaseOffset.cpp | 186 Register Rs = TailAdd.getOperand(1).getReg(); in foldLargeOffset() local
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| /llvm-project/clang/lib/Tooling/Core/ |
| H A D | Replacement.cpp | 222 Replacements Rs(R); in mergeIfOrderIndependent() local
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| /llvm-project/clang/lib/Headers/ |
| H A D | hvx_hexagon_protos.h | 30 #define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs) argument
4001 #define Q6_vgather_ARMVh(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)(Rs,Rt,Mu,Vv) argument
4012 #define Q6_vgather_AQRMVh(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) argument
4023 Q6_vgather_ARMWw(Rs,Rt,Mu,Vvv) global() argument
4034 Q6_vgather_AQRMWw(Rs,Qs,Rt,Mu,Vvv) global() argument
4045 Q6_vgather_ARMVw(Rs,Rt,Mu,Vv) global() argument
4056 Q6_vgather_AQRMVw(Rs,Qs,Rt,Mu,Vv) global() argument
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 1423 unsigned Rs = fieldFromInstruction(insn, 16, 5); DecodeExclusiveLdStInstruction() local
2065 unsigned Rs = fieldFromInstruction(insn, 16, 5); DecodeCPYMemOpInstruction() local
[all...] |