Lines Matching defs:Rs
279 // In memw(Rs+##V), the ##V could be replaced by a register Rt to
280 // form the rr mode: memw(Rt+Rs<<0). In such case, however, the
282 // another instruction memw(Rs+##V+4), it would need a different Rt.
283 // Now, if Rt was initialized as "##V+Rs<<0", both of these
290 // Include shifting the Rs to account for the ur addressing mode:
291 // ##Val + Rs << S
292 // ##Val - Rs
293 Register Rs;
298 ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {}
301 return Rs.Reg == 0;
304 return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg;
310 if (Rs != Ex.Rs)
311 return Rs < Ex.Rs;
446 : Rs(R), HRI(I) {}
447 HCE::Register Rs;
453 if (P.Rs.Reg != 0)
454 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub);
470 if (P.Ex.Rs.Reg != 0)
471 OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);
1167 case HexagonII::BaseImmOffset: // (__: ## + Rs<<0)
1172 ED.Expr.Rs = MI.getOperand(OpNum-1);
1174 case HexagonII::BaseLongOffset: // (__: ## + Rs<<S)
1175 ED.Expr.Rs = MI.getOperand(OpNum-2);
1196 case Hexagon::A2_addi: // (Rd: ## + Rs<<0)
1198 ED.Expr.Rs = MI.getOperand(OpNum-1);
1200 case Hexagon::M2_accii: // (__: ## + Rs<<0)
1203 ED.Expr.Rs = MI.getOperand(OpNum-1);
1205 case Hexagon::A2_subri: // (Rd: ## - Rs<<0)
1207 ED.Expr.Rs = MI.getOperand(OpNum+1);
1210 case Hexagon::S4_subaddi: // (__: ## - Rs<<0)
1211 ED.Expr.Rs = MI.getOperand(OpNum+1);
1240 case Hexagon::M2_macsin: // There is no Rx -= mpyi(Rs,Rt).
1465 return Extenders[I].Expr.Rs.isSlot();
1469 return ED.Expr.Rs.isSlot() == IsStack &&
1508 Register Rs = ExtI.second.Rs; // Only one reg allowed now.
1509 const MachineInstr *DefI = Rs.isVReg() ? MRI->getVRegDef(Rs.Reg) : nullptr;
1543 if (Ex.Rs.isSlot()) {
1548 .add(MachineOperand(Ex.Rs))
1551 assert((Ex.Rs.Reg == 0 || Ex.Rs.isVReg()) && "Expecting virtual register");
1561 .add(MachineOperand(Ex.Rs));
1565 .add(MachineOperand(Ex.Rs))
1575 .add(MachineOperand(Ex.Rs))
1583 .add(MachineOperand(Ex.Rs))
1678 // Loads: Rd = L4_loadri_ur Rs, S, ##
1679 // Stores: S4_storeri_ur Rs, S, ##, Rt
1784 assert(Ex.Rs == RegOp && EV == ImmOp && Ex.Neg != IsAddi &&
1796 // M2_accii: add(Rt,add(Rs,V)) (tied)
1797 // M2_naccii: sub(Rt,add(Rs,V))
1798 // S4_addaddi: add(Rt,add(Rs,V))
1799 // S4_subaddi: add(Rt,sub(V,Rs))
1800 // Check that Rs and V match the initializer expression. The Rs+V is the
1805 Register Rs = MI.getOperand(IsSub ? 3 : 2);
1807 assert(EV == V && Rs == Ex.Rs && IsSub == Ex.Neg && "Initializer mismatch");