/freebsd-src/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VVPISelLowering.cpp | 351 MVT ResVT = splitVectorType(Op.getValue(0).getSimpleValueType()); in splitVectorOp() local
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H A D | VECustomDAG.cpp | 562 SDValue VECustomDAG::getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, in getLegalReductionOpVVP()
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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 301 EVT ResVT = N->getValueType(0); ScalarizeVecRes_OverflowOp() local 1725 EVT ResVT = N->getValueType(0); SplitVecRes_OverflowOp() local 3146 EVT ResVT = N->getValueType(0); SplitVecOp_VECREDUCE() local 3165 EVT ResVT = N->getValueType(0); SplitVecOp_VECREDUCE_SEQ() local 3191 EVT ResVT = N->getValueType(0); SplitVecOp_VP_REDUCE() local 3215 EVT ResVT = N->getValueType(0); SplitVecOp_UnaryOp() local 3274 EVT ResVT = N->getValueType(0); SplitVecOp_INSERT_SUBVECTOR() local 3958 EVT ResVT = N->getValueType(0); SplitVecOp_FP_ROUND() local 4020 EVT ResVT = N->getValueType(0); SplitVecOp_FP_TO_XINT_SAT() local 4682 EVT ResVT = N->getValueType(0); WidenVecRes_OverflowOp() local 6231 EVT ResVT = WidenVecOp_IS_FPCLASS() local 6739 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), WidenVecOp_SETCC() local [all...] |
H A D | LegalizeIntegerTypes.cpp | 338 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); PromoteIntRes_Atomic0() local 2446 EVT ResVT = N->getValueType(0); PromoteIntOp_VECREDUCE() local 5543 EVT ResVT = V0.getValueType(); PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE() local 5922 EVT ResVT = N->getValueType(0); PromoteIntOp_CONCAT_VECTORS() local [all...] |
H A D | SelectionDAG.cpp | 2022 getStepVector(const SDLoc & DL,EVT ResVT) getStepVector() argument 2027 getStepVector(const SDLoc & DL,EVT ResVT,APInt StepVal) getStepVector() argument 12155 EVT ResVT = N->getValueType(0); UnrollVectorOverflowOp() local [all...] |
H A D | DAGCombiner.cpp | 8161 EVT ResVT = ExtractFrom.getValueType(); extractShiftForRotate() local 19111 EVT ResVT = Use->getValueType(0); canMergeExpensiveCrossRegisterBankCopy() local [all...] |
/freebsd-src/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 2495 EVT ResVT = N->getValueType(0); performVectorExtendToFPCombine() local 2529 EVT ResVT = N->getValueType(0); performVectorExtendCombine() local 2598 EVT ResVT; performVectorTruncZeroCombine() local 2645 EVT ResVT; performVectorTruncZeroCombine() local [all...] |
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 1759 EVT ResVT = TLI->getValueType(DL, ResTy); getExtendedReductionCost() local 1794 EVT ResVT = TLI->getValueType(DL, ResTy); getMulAccReductionCost() local
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H A D | ARMISelLowering.cpp | 17078 EVT ResVT = N->getValueType(0); PerformVECREDUCE_ADDCombine() local 21232 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument [all...] |
/freebsd-src/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 5693 EVT ResVT = N->getValueType(0); ReplaceLoadVector() local 5853 EVT ResVT = N->getValueType(0); ReplaceINTRINSIC_W_CHAIN() local [all...] |
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1788 shouldExpandGetActiveLaneMask(EVT ResVT,EVT OpVT) const shouldExpandGetActiveLaneMask() argument 5480 EVT ResVT = Op.getValueType(); LowerINTRINSIC_WO_CHAIN() local 16465 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument 20834 EVT ResVT; trySimplifySrlAddToRshrnb() local 20875 EVT ResVT = N->getValueType(0); performUzpCombine() local 21023 EVT ResVT = N->getValueType(0); performGLD1Combine() local 22820 EVT ResVT = N->getValueType(0); performVSelectCombine() local 22843 EVT ResVT = N->getValueType(0); performSelectCombine() local 26187 EVT ResVT = SrcVT.getVectorElementType(); LowerVECREDUCE_SEQ_FADD() local 26267 EVT ResVT = (Opcode == AArch64ISD::UADDV_PRED) ? MVT::i64 : LowerReductionToSVE() local [all...] |
/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | BasicTTIImpl.h | 1700 EVT ResVT = getTLI()->getValueType(DL, RetTy, true); getIntrinsicInstrCost() local
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H A D | TargetLowering.h | 3204 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) isExtractSubvectorCheap() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 3616 EVT ResVT = VA.getValVT(); fastLowerCall() local
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H A D | X86ISelLowering.cpp | 3105 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument 9075 MVT ResVT = Op.getSimpleValueType(); LowerAVXCONCAT_VECTORS() local 9143 MVT ResVT = Op.getSimpleValueType(); LowerCONCAT_VECTORSvXi1() local 19888 EVT ResVT = getSetCCResultType(DAG.getDataLayout(), FP_TO_INTHelper() local 20695 MVT ResVT = MVT::v4i32; LowerFP_TO_INT() local 20736 MVT ResVT = VT; LowerFP_TO_INT() local 20812 MVT ResVT = SrcVT == MVT::v4f64 ? MVT::v8i32 : MVT::v16i32; LowerFP_TO_INT() local 32188 EVT ResVT = getTypeToTransformTo(*DAG.getContext(), VT); ReplaceNodeResults() local 32408 EVT ResVT = EleVT == MVT::i32 ? MVT::v4i32 : MVT::v8i16; ReplaceNodeResults() local 43562 EVT ResVT = combineVPDPBUSDPattern() local 43637 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), ExtractVT, combineBasicSADPattern() local 46476 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts / 2); reduceVMULWidth() local 46696 MVT ResVT = MVT::getVectorVT(MVT::i32, Ops[0].getValueSizeInBits() / 32); combineMulToPMADDWD() local 51370 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i16, detectPMADDUBSW() local 54160 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, matchPMADDWD() local 54285 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, matchPMADDWD_2() local [all...] |
H A D | X86ISelDAGToDAG.cpp | 4895 MVT ResVT = Setcc.getSimpleValueType(); tryVPTESTM() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 3809 EVT ResVT = Op.getValueType(); lowerBITCAST() local 6462 combineExtract(const SDLoc & DL,EVT ResVT,EVT VecVT,SDValue Op,unsigned Index,DAGCombinerInfo & DCI,bool Force) const combineExtract() argument 6594 EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT); combineTruncateExtract() local [all...] |
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 2163 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 1867 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument 5511 auto ResVT = DAG.GetSplitDestVTs(VT); splitTernaryVectorOp() local 13081 EVT ResVT = N->getValueType(0); performExtractVectorEltCombine() local [all...] |
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 4594 EVT ResVT = VecVT.changeVectorElementTypeToInteger(); trySETCC() local
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H A D | PPCISelLowering.cpp | 8039 EVT ResVT = Op.getValueType(); LowerSELECT_CC() local 15156 EVT ResVT = Val.getValueType(); combineStoreFPToInt() local [all...] |
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 2140 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument 9180 lowerReductionSeq(unsigned RVVOpcode,MVT ResVT,SDValue StartValue,SDValue Vec,SDValue Mask,SDValue VL,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerReductionSeq() argument [all...] |