| /llvm-project/bolt/lib/Passes/ |
| H A D | RegAnalysis.cpp | 143 void RegAnalysis::getInstUsedRegsList(const MCInst &Inst, BitVector &RegSet, in getInstUsedRegsList()
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| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiDelaySlotFiller.cpp | 253 bool Filler::isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) { in isRegInSet()
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| /llvm-project/lldb/source/Plugins/Process/Linux/ |
| H A D | NativeRegisterContextLinux_x86_64.h | 72 enum class RegSet { gpr, fpu, avx, mpx }; enum
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| /llvm-project/llvm/lib/Target/Sparc/ |
| H A D | DelaySlotFiller.cpp | 343 IsRegInSet(SmallSet<unsigned,32> & RegSet,unsigned Reg) IsRegInSet() argument
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterPressure.h | 275 using RegSet = SparseSet<IndexMaskPair>; variable
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| /llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 41 const uint8_t *const RegSet; variable
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 258 SmallSet<unsigned, 4> RegSet; in AntiDepEdges() local
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| H A D | RegAllocPBQP.cpp | 149 using RegSet = std::set<Register>; global() typedef in __anon0dbd25830111::RegAllocPBQP
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| H A D | MachinePipeliner.cpp | 1469 __anon947477441002(RegSetTy &RegSet, Register Reg) computeMaxSetPressure() argument
1470 __anon947477441102(RegSetTy &RegSet, Register Reg) computeMaxSetPressure() argument
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| H A D | MachineVerifier.cpp | 124 using RegSet = DenseSet<Register>; global() typedef
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| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsDelaySlotFiller.cpp | 445 isRegInSet(const BitVector & RegSet,unsigned Reg) const isRegInSet() argument
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb1FrameLowering.cpp | 857 getNextOrderedReg(It OrderedStartIt,It OrderedEndIt,const std::set<Register> & RegSet) getNextOrderedReg() argument
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 553 for (Register R : RegSet) { in updateLiveness() argument
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