| /llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 170 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { in buildObjectGraph() argument
264 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) { in inheritRegUnits() argument
79 updateComponents(CodeGenRegBank & RegBank) updateComponents() argument
276 computeSubRegs(CodeGenRegBank & RegBank) computeSubRegs() argument
476 computeSecondarySubRegs(CodeGenRegBank & RegBank) computeSecondarySubRegs() argument
557 computeSuperRegs(CodeGenRegBank & RegBank) computeSuperRegs() argument
759 CodeGenRegisterClass(CodeGenRegBank & RegBank,Record * R) CodeGenRegisterClass() argument
842 CodeGenRegisterClass(CodeGenRegBank & RegBank,StringRef Name,Key Props) CodeGenRegisterClass() argument
857 inheritProperties(CodeGenRegBank & RegBank) inheritProperties() argument
1006 computeSubClasses(CodeGenRegBank & RegBank) computeSubClasses() argument
1058 getMatchingSubClassWithSubRegs(CodeGenRegBank & RegBank,const CodeGenSubRegIndex * SubIdx) const getMatchingSubClassWithSubRegs() argument
1153 buildRegUnitSet(const CodeGenRegBank & RegBank,std::vector<unsigned> & RegUnits) const buildRegUnitSet() argument
1169 CodeGenRegisterCategory(CodeGenRegBank & RegBank,Record * R) CodeGenRegisterCategory() argument
1726 computeUberSets(std::vector<UberRegSet> & UberSets,std::vector<UberRegSet * > & RegSets,CodeGenRegBank & RegBank) computeUberSets() argument
1785 computeUberWeights(std::vector<UberRegSet> & UberSets,CodeGenRegBank & RegBank) computeUberWeights() argument
1847 normalizeWeight(CodeGenRegister * Reg,std::vector<UberRegSet> & UberSets,std::vector<UberRegSet * > & RegSets,BitVector & NormalRegs,CodeGenRegister::RegUnitList & NormalUnits,CodeGenRegBank & RegBank) normalizeWeight() argument
[all...] |
| H A D | CodeGenTarget.h | 63 mutable std::unique_ptr<CodeGenRegBank> RegBank; variable
|
| H A D | CodeGenTarget.cpp | 180 getSuperRegForSubReg(const ValueTypeByHwMode & ValueTy,CodeGenRegBank & RegBank,const CodeGenSubRegIndex * SubIdx,bool MustBeAllocatable) const getSuperRegForSubReg() argument
|
| /llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 64 CodeGenRegBank &RegBank = Target.getRegBank(); RegisterInfoEmitter() local
208 EmitRegUnitPressure(raw_ostream & OS,const CodeGenRegBank & RegBank,const std::string & ClassName) EmitRegUnitPressure() argument
687 emitComposeSubRegIndices(raw_ostream & OS,CodeGenRegBank & RegBank,const std::string & ClName) emitComposeSubRegIndices() argument
756 emitComposeSubRegIndexLaneMask(raw_ostream & OS,CodeGenRegBank & RegBank,const std::string & ClName) emitComposeSubRegIndexLaneMask() argument
866 runMCDesc(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & RegBank) runMCDesc() argument
1106 runTargetHeader(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & RegBank) runTargetHeader() argument
1190 runTargetDesc(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & RegBank) runTargetDesc() argument
1804 CodeGenRegBank &RegBank = Target.getRegBank(); run() local
1822 CodeGenRegBank &RegBank = Target.getRegBank(); debugDump() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBankInfo.cpp | 73 const RegisterBank &RegBank = getRegBank(Idx); in verify() local
127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints() local
270 return hash_combine(StartIdx, Length, RegBank in hashPartialMapping() argument
[all...] |
| H A D | MachineRegisterInfo.cpp | 65 VRegInfo[Reg].first = &RegBank; in setRegBank() argument
|
| H A D | MachineVerifier.cpp | 2501 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg); visitMachineOperand() local
|
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass() local
358 unsigned RegBank, in selectLoadStoreOpCode() argument
1098 unsigned RegBank in select() local
[all...] |
| /llvm-project/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 46 const RegisterBank *RegBank; global() member
|
| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 61 const RegisterBank *RegBank; member
|
| /llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 204 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); getRegClass() local
1436 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); selectMergeValues() local
1505 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); materializeFP() local
|
| /llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 638 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); parseRegisterInfo() local
|
| H A D | MIParser.cpp | 294 const auto &RegBank = RBI->getRegBank(I); initNames2RegBanks() local
1604 const RegisterBank *RegBank = nullptr; parseRegisterClassOrBank() local
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1901 extendLow32IntoHigh32(MachineIRBuilder & B,Register Hi32Reg,Register Lo32Reg,unsigned ExtOpc,const RegisterBank & RegBank,bool IsBooleanSrc=false) extendLow32IntoHigh32() argument
3490 unsigned RegBank = AMDGPU::InvalidRegBankID; getMappingType() local
[all...] |
| H A D | SIInstrInfo.cpp | 9662 const RegisterBank *RegBank = RBI->getRegBank(Reg, MRI, RI); getInstructionUniformity() local
|
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 200 setRegBank(Register Reg,const RegisterBank * RegBank) setRegBank() argument
|