Lines Matching defs:RegBank

62   CodeGenRegBank &RegBank;
66       : Records(R), Target(R), RegBank(Target.getRegBank()) {
67     RegBank.computeDerivedInfo();
102   const auto &Registers = RegBank.getRegisters();
133   const auto &RegisterClasses = RegBank.getRegClasses();
167   auto &SubRegIndices = RegBank.getSubRegIndices();
186   unsigned NumSets = RegBank.getNumRegPressureSets();
188     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
204   unsigned NumRCs = RegBank.getRegClasses().size();
205   unsigned NumSets = RegBank.getNumRegPressureSets();
211   for (const auto &RC : RegBank.getRegClasses()) {
213     OS << "    {" << RC.getWeight(RegBank) << ", ";
218       RC.buildRegUnitSet(RegBank, RegUnits);
219       OS << RegBank.getRegUnitSetWeight(RegUnits);
230   for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
232     if (RegBank.getRegUnit(UnitIdx).Weight > 1)
238      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()
242     for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
244       const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
267     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
283     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
295   unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
299     ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
302       PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order);
334      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()
338   for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
340     OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])
682   const auto &SubRegIndices = RegBank.getSubRegIndices();
751   const auto &SubRegIndices = RegBank.getSubRegIndices();
864   const auto &Regs = RegBank.getRegisters();
866   auto &SubRegIndices = RegBank.getSubRegIndices();
898     Reg.addSubRegsPreOrder(SR, RegBank);
979   for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
980     ArrayRef<const CodeGenRegister *> Roots = RegBank.getRegUnit(i).getRoots();
991   const auto &RegisterClasses = RegBank.getRegClasses();
1020         BVE.add(RegBank.getReg(Reg)->EnumValue);
1081      << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
1114   if (!RegBank.getSubRegIndices().empty()) {
1152   const auto &RegisterClasses = RegBank.getRegClasses();
1193   const auto &RegisterClasses = RegBank.getRegClasses();
1194   const auto &SubRegIndices = RegBank.getSubRegIndices();
1428   const auto &Regs = RegBank.getRegisters();
1536             MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, &Idx);
1640   printMask(OS, RegBank.CoveringLanes);
1646      << "                     " << RegBank.getNumNativeRegUnits() << ",\n"
1663     const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1673     BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1680       RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
1681       Covered |= RegBank.computeCoveredRegisters(OPSet.getArrayRef());
1686     for (const auto &Reg : RegBank.getRegisters()) {
1690     Covered |= RegBank.computeCoveredRegisters(ConstantSet.getArrayRef());
1712       RegBank.getRegCategories();
1829   for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {
1851     for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) {
1864   for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) {
1877   for (const CodeGenRegister &R : RegBank.getRegisters()) {