| /freebsd-src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | |
| H A D | RegisterInfoEmitter.cpp | 64 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local
209 EmitRegUnitPressure(raw_ostream & OS,const CodeGenRegBank & RegBank,const std::string & ClassName) EmitRegUnitPressure() argument
695 emitComposeSubRegIndices(raw_ostream & OS,CodeGenRegBank & RegBank,const std::string & ClName) emitComposeSubRegIndices() argument
765 emitComposeSubRegIndexLaneMask(raw_ostream & OS,CodeGenRegBank & RegBank,const std::string & ClName) emitComposeSubRegIndexLaneMask() argument
872 runMCDesc(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & RegBank) runMCDesc() argument
1121 runTargetHeader(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & RegBank) runTargetHeader() argument
1204 runTargetDesc(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & RegBank) runTargetDesc() argument
1808 CodeGenRegBank &RegBank = Target.getRegBank(); run() local
1826 CodeGenRegBank &RegBank = Target.getRegBank(); debugDump() local
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| H A D | CodeGenTarget.h | |
| H A D | CodeGenTarget.cpp | |
| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBankInfo.cpp | 73 const RegisterBank &RegBank = getRegBank(Idx); in verify() local
127 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); in getRegBankFromConstraints() local
270 const RegisterBank *RegBank) { in hashPartialMapping() argument
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| H A D | MachineRegisterInfo.cpp | 63 setRegBank(Register Reg,const RegisterBank & RegBank) setRegBank() argument
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| H A D | MachineVerifier.cpp | 2276 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg); visitMachineOperand() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); guessRegClass() local
356 selectLoadStoreOpCode(unsigned Opc,unsigned RegBank,unsigned Size) const selectLoadStoreOpCode() argument
1087 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID(); select() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 46 const RegisterBank *RegBank; member
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 61 const RegisterBank *RegBank; member
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 206 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); getRegClass() local
1419 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); selectMergeValues() local
1488 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); materializeFP() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 619 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); parseRegisterInfo() local
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| H A D | MIParser.cpp | 294 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks() local
1598 const RegisterBank *RegBank = nullptr; parseRegisterClassOrBank() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1901 extendLow32IntoHigh32(MachineIRBuilder & B,Register Hi32Reg,Register Lo32Reg,unsigned ExtOpc,const RegisterBank & RegBank,bool IsBooleanSrc=false) extendLow32IntoHigh32() argument
3484 unsigned RegBank = AMDGPU::InvalidRegBankID; getMappingType() local
[all...] |
| H A D | SIInstrInfo.cpp | 9546 const RegisterBank *RegBank = RBI->getRegBank(Reg, MRI, RI); getInstructionUniformity() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 197 setRegBank(Register Reg,const RegisterBank * RegBank) setRegBank() argument
|