Lines Matching defs:RegBank
64 CodeGenRegBank &RegBank = Target.getRegBank();
65 RegBank.computeDerivedInfo();
93 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
95 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
97 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
208 const CodeGenRegBank &RegBank,
210 unsigned NumRCs = RegBank.getRegClasses().size();
211 unsigned NumSets = RegBank.getNumRegPressureSets();
217 for (const auto &RC : RegBank.getRegClasses()) {
219 OS << " {" << RC.getWeight(RegBank) << ", ";
224 RC.buildRegUnitSet(RegBank, RegUnits);
225 OS << RegBank.getRegUnitSetWeight(RegUnits);
236 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
238 if (RegBank.getRegUnit(UnitIdx).Weight > 1)
244 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
248 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
250 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
273 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
289 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
301 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
305 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
308 PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order);
340 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
344 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
346 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])
687 CodeGenRegBank &RegBank,
689 const auto &SubRegIndices = RegBank.getSubRegIndices();
756 raw_ostream &OS, CodeGenRegBank &RegBank, const std::string &ClName) {
758 const auto &SubRegIndices = RegBank.getSubRegIndices();
866 CodeGenRegBank &RegBank) {
872 const auto &Regs = RegBank.getRegisters();
874 auto &SubRegIndices = RegBank.getSubRegIndices();
905 Reg.addSubRegsPreOrder(SR, RegBank);
988 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
989 ArrayRef<const CodeGenRegister *> Roots = RegBank.getRegUnit(i).getRoots();
1000 const auto &RegisterClasses = RegBank.getRegClasses();
1090 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
1106 CodeGenRegBank &RegBank) {
1125 if (!RegBank.getSubRegIndices().empty()) {
1161 const auto &RegisterClasses = RegBank.getRegClasses();
1190 CodeGenRegBank &RegBank) {
1203 const auto &RegisterClasses = RegBank.getRegClasses();
1204 const auto &SubRegIndices = RegBank.getSubRegIndices();
1440 const auto &Regs = RegBank.getRegisters();
1493 emitComposeSubRegIndices(OS, RegBank, ClassName);
1494 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName);
1548 MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, &Idx);
1576 EmitRegUnitPressure(OS, RegBank, ClassName);
1652 printMask(OS, RegBank.CoveringLanes);
1658 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1676 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1686 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1693 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
1694 Covered |= RegBank.computeCoveredRegisters(
1700 for (auto &Reg : RegBank.getRegisters()) {
1704 Covered |= RegBank.computeCoveredRegisters(
1727 RegBank.getRegCategories();
1804 CodeGenRegBank &RegBank = Target.getRegBank();
1806 runEnums(OS, Target, RegBank);
1809 runMCDesc(OS, Target, RegBank);
1812 runTargetHeader(OS, Target, RegBank);
1815 runTargetDesc(OS, Target, RegBank);
1822 CodeGenRegBank &RegBank = Target.getRegBank();
1831 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {
1853 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) {
1866 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) {
1879 for (const CodeGenRegister &R : RegBank.getRegisters()) {