| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86DynAllocaExpander.cpp | 224 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; lower() local
238 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; lower() local
251 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX; lower() local
|
| H A D | X86RegisterInfo.cpp | 674 __anonbd65f2650102(MCRegister RegA, MCRegister RegB) isArgumentRegister() argument
681 __anonbd65f2650202(MCRegister &RegA) isArgumentRegister() argument
691 __anonbd65f2650302(MCRegister &RegA) isArgumentRegister() argument
696 __anonbd65f2650402(MCRegister &RegA) isArgumentRegister() argument
703 __anonbd65f2650502(MCRegister &RegA) isArgumentRegister() argument
[all...] |
| /llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 482 /// Returns true if RegB is a sub-register of RegA. in isSuperRegisterEq() argument
488 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const; in isSuperOrSubRegisterEq() argument
468 isSubRegister(MCRegister RegA,MCRegister RegB) isSubRegister() argument
476 isSubRegisterEq(MCRegister RegA,MCRegister RegB) isSubRegisterEq() argument
610 isSuperRegister(MCRegister RegA,MCRegister RegB) isSuperRegister() argument
[all...] |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 471 regsAreCompatible(Register RegA,Register RegB) const regsAreCompatible() argument
560 isProfitableToCommute(Register RegA,Register RegB,Register RegC,MachineInstr * MI,unsigned Dist) isProfitableToCommute() argument
687 Register RegA = MI->getOperand(DstIdx).getReg(); commuteInstruction() local
696 isProfitableToConv3Addr(Register RegA,Register RegB) isProfitableToConv3Addr() argument
715 convertInstTo3Addr(MachineBasicBlock::iterator & mi,MachineBasicBlock::iterator & nmi,Register RegA,Register RegB,unsigned & Dist) convertInstTo3Addr() argument
1501 Register RegA = DstMO.getReg(); processTiedPairs() local
1686 Register RegA = DstMO.getReg(); processStatepoint() local
[all...] |
| H A D | ImplicitNullChecks.cpp | 286 Register RegA = MOA.getReg(); in canReorder() local
|
| H A D | TargetInstrInfo.cpp | 1099 Register RegA = OpA.getReg(); reassociateOps() local
|
| /llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 207 regsOverlap(MCRegister RegA,MCRegister RegB) const regsOverlap() argument
|
| /llvm-project/llvm/unittests/Analysis/ |
| H A D | SparsePropagation.cpp | 480 auto RegA = TestLatticeKey(A, IPOGrouping::Register); TEST_F() local
|
| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 449 regsOverlap(Register RegA,Register RegB) regsOverlap() argument
|
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2224 for (auto &RegA : DefsA) isDependent() local
|
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 510 Register RegA = Prev->getOperand(AddOpIdx).getReg(); getFMAPatterns() local
|
| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 6935 Register RegA = Root.getOperand(1).getReg(); genSubAdd2SubSub() local
|