Lines Matching defs:RegA

141   bool regsAreCompatible(Register RegA, Register RegB) const;
150   bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
156   bool isProfitableToConv3Addr(Register RegA, Register RegB);
159                           MachineBasicBlock::iterator &nmi, Register RegA,
544 bool TwoAddressInstructionImpl::regsAreCompatible(Register RegA,
546   if (RegA == RegB)
548   if (!RegA || !RegB)
550   return TRI->regsOverlap(RegA, RegB);
633 bool TwoAddressInstructionImpl::isProfitableToCommute(Register RegA,
672   MCRegister ToRegA = getMappedReg(RegA, DstRegMap);
680     // -RegB is not tied to a register and RegC is compatible with RegA.
686     // -RegC is not tied to a register and RegB is compatible with RegA.
720   if (isRevCopyChain(RegC, RegA, MaxDataFlowEdge))
723   if (isRevCopyChain(RegB, RegA, MaxDataFlowEdge))
760     Register RegA = MI->getOperand(DstIdx).getReg();
761     SrcRegMap[RegA] = FromRegC;
769 bool TwoAddressInstructionImpl::isProfitableToConv3Addr(Register RegA,
780   MCRegister ToRegA = getMappedReg(RegA, DstRegMap);
788     Register RegA, Register RegB, unsigned &Dist) {
821   SrcRegMap.erase(RegA);
1571     Register RegA = DstMO.getReg();
1578     if (RegA == RegB) {
1585     LastCopiedReg = RegA;
1596              MI->getOperand(i).getReg() != RegA);
1601                                       TII->get(TargetOpcode::COPY), RegA);
1607       if (RegA.isVirtual()) {
1608         assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1614         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1630       if (RegA.isVirtual()) {
1631         LiveInterval &LI = LIS->getInterval(RegA);
1639         for (MCRegUnit Unit : TRI->regunits(RegA)) {
1660     if (RegA.isVirtual() && RegB.isVirtual())
1661       MRI->constrainRegClass(RegA, RC);
1662     MO.setReg(RegA);
1664     // by SubRegB is compatible with RegA with no subregister. So regardless of
1735 //    RegA = STATEPOINT ... RegB(tied-def N)
1738 // and replaces all uses of RegA with RegB.
1756     Register RegA = DstMO.getReg();
1760     if (RegA == RegB)
1770       const auto &DefLI = LIS->getInterval(RegA);
1787     if (!MRI->constrainRegClass(RegB, MRI->getRegClass(RegA))) {
1789                         << " to register class of " << printReg(RegA, TRI, 0)
1794     MRI->replaceRegWith(RegA, RegB);
1799       LiveInterval &Other = LIS->getInterval(RegA);
1810       LIS->removeInterval(RegA);
1817       LiveVariables::VarInfo &DstInfo = LV->getVarInfo(RegA);