| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 837 EmitInstrRegReg(const MCSubtargetInfo & STI,unsigned Opcode,unsigned Reg1,unsigned Reg2) EmitInstrRegReg() argument
857 EmitInstrRegRegReg(const MCSubtargetInfo & STI,unsigned Opcode,unsigned Reg1,unsigned Reg2,unsigned Reg3) EmitInstrRegRegReg() argument
868 EmitMovFPIntPair(const MCSubtargetInfo & STI,unsigned MovOpc,unsigned Reg1,unsigned Reg2,unsigned FPReg1,unsigned FPReg2,bool LE) EmitMovFPIntPair() argument
[all...] |
| H A D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
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| H A D | MipsISelLowering.cpp | 2978 unsigned Reg2 = State.AllocateReg(IntRegs); CC_MipsO32() local
3712 unsigned Reg2 = LowerFormalArguments() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 204 emitStore(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator Pos,const TargetInstrInfo & TII,unsigned Reg1,unsigned Reg2,int Offset,bool IsPreDec) emitStore() argument
245 emitLoad(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator Pos,const TargetInstrInfo & TII,unsigned Reg1,unsigned Reg2,int Offset,bool IsPostDec) emitLoad() argument
[all...] |
| H A D | AArch64FrameLowering.cpp | 2703 invalidateWindowsRegisterPairing(unsigned Reg1,unsigned Reg2,bool NeedsWinCFI,bool IsFirst,const TargetRegisterInfo * TRI) invalidateWindowsRegisterPairing() argument
2734 invalidateRegisterPairing(unsigned Reg1,unsigned Reg2,bool UsesWinAAPCS,bool NeedsWinCFI,bool NeedsFrameRecord,bool IsFirst,const TargetRegisterInfo * TRI) invalidateRegisterPairing() argument
2754 unsigned Reg2 = AArch64::NoRegister; global() member
3007 unsigned Reg2 = RPI.Reg2; spillCalleeSavedRegisters() local
3113 unsigned Reg2 = RPI.Reg2; restoreCalleeSavedRegisters() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXFMAMutate.cpp | 190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock() local
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| H A D | PPCVSXSwapRemoval.cpp | 899 Register Reg2 = MI->getOperand(2).getReg(); in handleSpecialSwappables() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 166 unsigned Reg2, bool isKill2) { in addRegReg()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/ |
| H A D | CSKYMCCodeEmitter.cpp | 270 unsigned Reg2 = in getRegisterSeqOpValue() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 758 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
793 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
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| H A D | A15SDOptimizer.cpp | 446 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
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| H A D | ARMFastISel.cpp | 2800 unsigned Reg2 = 0; in SelectShift() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 990 bool &HaveReg2, Register &Reg2, in parseAddress() argument
1102 Register Reg1, Reg2; in parseAddress() local
1495 Register Reg1, Reg2; parseOperand() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 686 unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true); generateCompactUnwindEncoding() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 82 contains(MCRegister Reg1,MCRegister Reg2) contains() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 89 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { in UnionGroups() argument
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| H A D | MachineInstr.cpp | 2456 Register Reg2 = getOperand(2).getReg(); getFirst3RegLLTs() local
2466 Register Reg2 = getOperand(2).getReg(); getFirst4RegLLTs() local
2478 Register Reg2 = getOperand(2).getReg(); getFirst5RegLLTs() local
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| H A D | TargetInstrInfo.cpp | 187 Register Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 227 unsigned Reg2, SMLoc IDLoc, in emitRRR() argument
233 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, in emitRRRX() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1758 StringRef Reg2(R2); processInstruction() local
1902 StringRef Reg2(R2); processInstruction() local
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 105 contains(Register Reg1,Register Reg2) contains() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 1466 MCRegister Reg2; in parseOperand() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCDwarf.cpp | 1329 unsigned Reg2 = Instr.getRegister2(); emitCFIInstruction() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 383 MCRegister Reg2; global() member
2476 MCRegister Reg2 = matchRegisterNameHelper(isRVE(), Reg2Name); parseRegReg() local
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| /freebsd-src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | |