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Searched defs:Reg1 (Results 1 – 25 of 54) sorted by relevance

123

/llvm-project/clang-tools-extra/test/clang-tidy/checkers/llvm/
H A Dprefer-register-over-unsigned.cpp24 unsigned Reg1 = getReg(); in apply_1() local
52 llvm::Register Reg1 = getReg(); in done_1() local
74 unsigned Reg1 = getRegLike(); in do_nothing_1() local
H A Dprefer-register-over-unsigned3.cpp14 unsigned Reg1 = getReg(); in do_nothing_1() local
/llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/
H A DTargetTest.cpp91 const unsigned Reg1 = Mips::T1; in TEST_F() local
103 const unsigned Reg1 = Mips::T1_64; in TEST_F() local
/llvm-project/llvm/unittests/DebugInfo/DWARF/
H A DDWARFDebugFrameTest.cpp1001 constexpr uint8_t Reg1 = 14; TEST() local
1057 constexpr uint8_t Reg1 = 14; TEST() local
1107 constexpr uint8_t Reg1 = 14; TEST() local
1148 constexpr uint8_t Reg1 = 14; TEST() local
1265 constexpr uint8_t Reg1 = 14; TEST() local
1310 constexpr uint8_t Reg1 = 14; TEST() local
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/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp199 emitRR(unsigned Opcode,unsigned Reg0,unsigned Reg1,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRR() argument
214 emitRRX(unsigned Opcode,unsigned Reg0,unsigned Reg1,MCOperand Op2,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRX() argument
226 emitRRR(unsigned Opcode,unsigned Reg0,unsigned Reg1,unsigned Reg2,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRR() argument
232 emitRRRX(unsigned Opcode,unsigned Reg0,unsigned Reg1,unsigned Reg2,MCOperand Op3,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRRX() argument
245 emitRRI(unsigned Opcode,unsigned Reg0,unsigned Reg1,int16_t Imm,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRI() argument
252 emitRRIII(unsigned Opcode,unsigned Reg0,unsigned Reg1,int16_t Imm0,int16_t Imm1,int16_t Imm2,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRIII() argument
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/llvm-project/llvm/lib/Target/X86/
H A DX86CompressEVEX.cpp198 if (Reg1 == Reg0) in CompressEVEXImpl() local
H A DX86InstrBuilder.h165 unsigned Reg1, bool isKill1, in addRegReg()
H A DX86ExpandPseudo.cpp468 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1); expandMI() local
504 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1); expandMI() local
/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsSizeReduction.cpp378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr() local
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP() local
H A DMipsAsmPrinter.cpp840 EmitInstrRegReg(const MCSubtargetInfo & STI,unsigned Opcode,unsigned Reg1,unsigned Reg2) EmitInstrRegReg() argument
860 EmitInstrRegRegReg(const MCSubtargetInfo & STI,unsigned Opcode,unsigned Reg1,unsigned Reg2,unsigned Reg3) EmitInstrRegRegReg() argument
871 EmitMovFPIntPair(const MCSubtargetInfo & STI,unsigned MovOpc,unsigned Reg1,unsigned Reg2,unsigned FPReg1,unsigned FPReg2,bool LE) EmitMovFPIntPair() argument
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H A DMipsSEFrameLowering.cpp464 unsigned Reg1 = emitPrologue() local
481 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; emitPrologue() local
H A DMips16InstrInfo.cpp278 adjustStackPtrBig(unsigned SP,int64_t Amount,MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned Reg1,unsigned Reg2) const adjustStackPtrBig() argument
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp205 emitStore(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator Pos,const TargetInstrInfo & TII,unsigned Reg1,unsigned Reg2,int Offset,bool IsPreDec) emitStore() argument
246 emitLoad(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator Pos,const TargetInstrInfo & TII,unsigned Reg1,unsigned Reg2,int Offset,bool IsPostDec) emitLoad() argument
H A DAArch64FrameLowering.cpp1315 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH() local
1219 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); InsertSEH() local
1232 Register Reg1 = MBBI->getOperand(2).getReg(); InsertSEH() local
1270 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); InsertSEH() local
1281 Register Reg1 = MBBI->getOperand(1).getReg(); InsertSEH() local
1328 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); InsertSEH() local
2782 invalidateWindowsRegisterPairing(unsigned Reg1,unsigned Reg2,bool NeedsWinCFI,bool IsFirst,const TargetRegisterInfo * TRI) invalidateWindowsRegisterPairing() argument
2813 invalidateRegisterPairing(unsigned Reg1,unsigned Reg2,bool UsesWinAAPCS,bool NeedsWinCFI,bool NeedsFrameRecord,bool IsFirst,const TargetRegisterInfo * TRI) invalidateRegisterPairing() argument
2832 unsigned Reg1 = AArch64::NoRegister; global() member
3101 unsigned Reg1 = RPI.Reg1; spillCalleeSavedRegisters() local
3344 unsigned Reg1 = RPI.Reg1; restoreCalleeSavedRegisters() local
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/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp346 Register Reg1 = Op1.getReg(); legalizeCustom() local
/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.cpp93 unsigned Reg1; adjustStackPtr() local
/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp268 unsigned Reg1 = in getRegisterSeqOpValue() local
/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp235 Register Reg1 = cast<RegisterSDNode>(V1)->getReg(); tryInlineAsm() local
/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h83 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
702 uint16_t Reg1 = 0; global() variable
/llvm-project/llvm/unittests/CodeGen/GlobalISel/
H A DCSETest.cpp79 Register Reg1 = MRI->createGenericVirtualRegister(s32); TEST_F() local
H A DPatternMatchTest.cpp298 Register Reg1; TEST_F() local
323 Register Reg1; TEST_F() local
/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp201 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in selectInlineAsm() local
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp980 Register Reg1 = Reg; lowerCRSpilling() local
1025 Register Reg1 = Reg; lowerCRRestore() local
1139 Register Reg1 = Reg; lowerCRBitSpilling() local
/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp446 createRegSequence(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,const DebugLoc & DL,unsigned Reg1,unsigned Reg2) createRegSequence() argument
/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp2523 Register Reg1 = getOperand(1).getReg(); getFirst2RegLLTs() local
2531 Register Reg1 = getOperand(1).getReg(); getFirst3RegLLTs() local
2541 Register Reg1 = getOperand(1).getReg(); getFirst4RegLLTs() local
2553 Register Reg1 = getOperand(1).getReg(); getFirst5RegLLTs() local
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