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Searched defs:Reg1 (Results 1 – 25 of 45) sorted by relevance

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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp199 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
214 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
226 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR() argument
232 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX() argument
245 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI() argument
252 emitRRIII(unsigned Opcode,unsigned Reg0,unsigned Reg1,int16_t Imm0,int16_t Imm1,int16_t Imm2,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRIII() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp1191 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); InsertSEH() local
1204 Register Reg1 = MBBI->getOperand(2).getReg(); InsertSEH() local
1242 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); InsertSEH() local
1253 Register Reg1 = MBBI->getOperand(1).getReg(); InsertSEH() local
1287 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); InsertSEH() local
1300 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); InsertSEH() local
2703 invalidateWindowsRegisterPairing(unsigned Reg1,unsigned Reg2,bool NeedsWinCFI,bool IsFirst,const TargetRegisterInfo * TRI) invalidateWindowsRegisterPairing() argument
2734 invalidateRegisterPairing(unsigned Reg1,unsigned Reg2,bool UsesWinAAPCS,bool NeedsWinCFI,bool NeedsFrameRecord,bool IsFirst,const TargetRegisterInfo * TRI) invalidateRegisterPairing() argument
2753 unsigned Reg1 = AArch64::NoRegister; global() member
3006 unsigned Reg1 = RPI.Reg1; spillCalleeSavedRegisters() local
3112 unsigned Reg1 = RPI.Reg1; restoreCalleeSavedRegisters() local
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H A DAArch64LowerHomogeneousPrologEpilog.cpp204 emitStore(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator Pos,const TargetInstrInfo & TII,unsigned Reg1,unsigned Reg2,int Offset,bool IsPreDec) emitStore() argument
245 emitLoad(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator Pos,const TargetInstrInfo & TII,unsigned Reg1,unsigned Reg2,int Offset,bool IsPostDec) emitLoad() argument
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp836 EmitInstrRegReg(const MCSubtargetInfo & STI,unsigned Opcode,unsigned Reg1,unsigned Reg2) EmitInstrRegReg() argument
856 EmitInstrRegRegReg(const MCSubtargetInfo & STI,unsigned Opcode,unsigned Reg1,unsigned Reg2,unsigned Reg3) EmitInstrRegRegReg() argument
867 EmitMovFPIntPair(const MCSubtargetInfo & STI,unsigned MovOpc,unsigned Reg1,unsigned Reg2,unsigned FPReg1,unsigned FPReg2,bool LE) EmitMovFPIntPair() argument
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H A DMicroMipsSizeReduction.cpp378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr() local
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP() local
H A DMipsSEFrameLowering.cpp464 unsigned Reg1 = emitPrologue() local
481 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; emitPrologue() local
H A DMips16InstrInfo.cpp278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ExpandPseudo.cpp468 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1); in ExpandMI() local
506 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1); ExpandMI() local
H A DX86CompressEVEX.cpp194 Register Reg1 = Op1.getReg(); isRedundantNewDataDest() local
H A DX86InstrBuilder.h165 unsigned Reg1, bool isKill1, in addRegReg()
H A DX86AvoidStoreForwardingBlocks.cpp391 Register Reg1 = MRI->createVirtualRegister( in buildCopy() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp303 Register Reg1 = Op1.getReg(); legalizeCustom() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp229 Register Reg1 = cast<RegisterSDNode>(V1)->getReg(); tryInlineAsm() local
/freebsd-src/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h82 contains(MCRegister Reg1,MCRegister Reg2) contains() argument
705 uint16_t Reg1 = 0; global() variable
/freebsd-src/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp268 unsigned Reg1 = in getRegisterSeqOpValue() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp980 Register Reg1 = Reg; in lowerCRSpilling() local
1025 Register Reg1 = Reg; in lowerCRRestore() local
1139 Register Reg1 = Reg; in lowerCRBitSpilling() local
H A DPPCVSXSwapRemoval.cpp898 Register Reg1 = MI->getOperand(1).getReg(); in handleSpecialSwappables() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp194 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); selectInlineAsm() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp1463 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); printVectorListTwo() local
1476 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); printVectorListTwoSpaced() local
1531 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); printVectorListTwoAllLanes() local
1578 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); printVectorListTwoSpacedAllLanes() local
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp2447 Register Reg1 = getOperand(1).getReg(); getFirst2RegLLTs() local
2455 Register Reg1 = getOperand(1).getReg(); getFirst3RegLLTs() local
2465 Register Reg1 = getOperand(1).getReg(); getFirst4RegLLTs() local
2477 Register Reg1 = getOperand(1).getReg(); getFirst5RegLLTs() local
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H A DAggressiveAntiDepBreaker.cpp89 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { in UnionGroups() argument
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp446 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
H A DThumb2SizeReduction.cpp755 Register Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp989 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, in parseAddress() argument
1102 Register Reg1, Reg2; in parseAddress() local
1495 Register Reg1, Reg2; parseOperand() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp675 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); generateCompactUnwindEncoding() local
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