Lines Matching defs:Reg1
427 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
988 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
989 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
1017 // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1018 // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
1028 if (parseRegister(Reg1))
1047 if (parseIntegerRegister(Reg1, RegGroup))
1102 Register Reg1, Reg2;
1109 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1122 // If we have Reg1, it must be an address register.
1124 if (parseAddressRegister(Reg1))
1126 Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
1133 // If we have Reg1, it must be an address register.
1135 if (parseAddressRegister(Reg1))
1140 Index = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
1142 Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
1166 // We must have Reg1, and it must be a GPR.
1167 if (!HaveReg1 || Reg1.Group != RegGR)
1169 LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1178 // We must have Reg1, and it must be a vector register.
1179 if (!HaveReg1 || Reg1.Group != RegV)
1181 Index = SystemZMC::VR128Regs[Reg1.Num];
1495 Register Reg1, Reg2;
1499 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1504 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1505 && parseAddressRegister(Reg1))