| /netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| H A D | a3.s | 8 R0 = W [ P1 + -2 ] (Z); DBGA ( R0.L , 49 ); define
9 R0 = W [ P1 + -4 ] (Z); DBGA ( R0.L , 48 ); define
10 R0 = W [ P1 + -6 ] (Z); DBGA ( R0.L , 47 ); define
11 R0 = W [ P1 + -8 ] (Z); DBGA ( R0.L , 46 ); define
12 R0 = W [ P1 + -10 ] (Z); DBGA ( R0.L , 45 ); define
13 R0 = W [ P1 + -12 ] (Z); DBGA ( R0.L , 44 ); define
14 R0 = W [ P1 + -14 ] (Z); DBGA ( R0.L , 43 ); define
15 R0 = W [ P1 + -16 ] (Z); DBGA ( R0.L , 42 ); define
16 R0 = W [ P1 + -18 ] (Z); DBGA ( R0.L , 41 ); define
17 R0 = W [ P1 + -20 ] (Z); DBGA ( R0.L , 40 ); define
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| H A D | a2.s | 8 R0 = [ P0 + 0 ]; DBGA ( R0.L , 50 ); define
9 R0 = [ P0 + 4 ]; DBGA ( R0.L , 51 ); define
10 R0 = [ P0 + 8 ]; DBGA ( R0.L , 52 ); define
11 R0 = [ P0 + 12 ]; DBGA ( R0.L , 53 ); define
12 R0 = [ P0 + 16 ]; DBGA ( R0.L , 54 ); define
13 R0 = [ P0 + 20 ]; DBGA ( R0.L , 55 ); define
14 R0 = [ P0 + 24 ]; DBGA ( R0.L , 56 ); define
15 R0 = [ P0 + 28 ]; DBGA ( R0.L , 57 ); define
17 R0 = [ P0 + -4 ]; DBGA ( R0.L , 49 ); define
18 R0 = [ P0 + -8 ]; DBGA ( R0.L , 48 ); define
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| H A D | a11.S | 15 R0 = 0xfff0 (Z); define
18 R0 = ASTAT; define
28 R0 = ASTAT; define
38 R0 = ASTAT; define
51 R0 = ASTAT; define
61 R0 = ASTAT; define
71 R0 = ASTAT; define
81 R0 = ASTAT; define
97 R0 = ASTAT; define
111 R0 = ASTAT; define
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| H A D | lmu_cplb_multiple0.S | 31 R0 = 0; define
156 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
180 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
204 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
228 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
252 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
276 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
300 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
324 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
348 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
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| H A D | lmu_cplb_multiple1.S | 31 R0 = 0; define
158 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
182 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
206 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
230 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
254 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
278 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
302 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
326 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
350 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
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| H A D | a21.s | 9 R0 = 0xffffffff; define
12 R0 = 0x7f (X); define
20 R0 = 0; define
23 R0 = 0x80 (X); define
31 R0 = 0xfffffff0; define
34 R0 = 0x01; define
42 R0 = 0xfffffff0; define
45 R0 = 0x01; define
53 R0 = 0x00000001; define
55 R0 = 0xffffffff; define
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| H A D | stk6.s | 31 R0 = P0; DBGA ( R0.L , 9 ); define
32 R0 = P1; DBGA ( R0.L , 10 ); define
33 R0 = P2; DBGA ( R0.L , 11 ); define
34 R0 = P3; DBGA ( R0.L , 12 ); define
35 R0 = P4; DBGA ( R0.L , 13 ); define
36 R0 = P5; DBGA ( R0.L , 14 ); define
37 R0 = 1; define
50 R0 = P0; DBGA ( R0.L , 9 ); define
51 R0 = P1; DBGA ( R0.L , 10 ); define
52 R0 = P2; DBGA ( R0.L , 11 ); define
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| H A D | s11.s | 25 R0 = A0.w; define
30 R0 = CC; define
43 R0 = A0.w; define
48 R0 = CC; define
61 R0 = A0.w; define
66 R0 = CC; define
80 R0 = A0.w; define
85 R0 = CC; define
106 R0 = A0.w; define
126 R0 = A0.w; define
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| H A D | c_dsp32shift_bitmux.s | 35 R0 = A0.w; define
65 R0 = A0.w; define
95 R0 = A0.w; define
125 R0 = A0.w; define
155 R0 = A0.w; define
185 R0 = A0.w; define
215 R0 = A0.w; define
245 R0 = A0.w; define
275 R0 = A0.w; define
305 R0 = A0.w; define
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| H A D | a0shift.S | 46 R0 = A1.w define
48 R0 = A1.x define
50 R0 = A0.w define
52 R0 = A0.x define
70 R0 = A1.w define
72 R0 = A1.x define
74 R0 = A0.w define
76 R0 = A0.x define
88 R0 = A1.w define
90 R0 = A1.x define
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| H A D | b0.S | 7 R0 = 0; define
14 R0 = ASTAT; CHECKREG R0, (_AC0|_AC0_COPY|_CC|_AZ); define
15 R0 = R0 + R0; define
16 R0 = ASTAT; CHECKREG R0, (_CC); define
19 R0 = ASTAT; CHECKREG R0, (_CC|_AN); define
20 R0 = - R0; define
21 R0 = ASTAT; CHECKREG R0, (_CC|_AN); define
25 R0 = ASTAT; CHECKREG R0, (_AC0|_CC|_AN); define
29 R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_CC|_AN); define
33 R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_CC|_AN); define
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| H A D | a23.s | 8 R0 = 0x00000000; define
10 R0 = 0x80 (X); define
19 R0 = 0x00000001; define
21 R0 = 0x80 (X); define
30 R0 = 0xffffffff; define
32 R0 = 0xff (X); define
41 R0 = 0xfffffff0; define
43 R0 = 0x7f (X); define
52 R0 = 0x00000000; define
54 R0 = 0x80 (X); define
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| H A D | a22.s | 8 R0 = 0xffffffff; define
10 R0 = 0x7f (X); define
19 R0 = 0x1; define
21 R0 = 0x0; define
30 R0 = 0xffffffff; define
32 R0 = 0xff (X); define
40 R0 = 0x00000000; define
42 R0 = 0x80 (X); define
51 R0 = 0x00000000; define
53 R0 = 0x80 (X); define
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| H A D | testset2.s | 15 R0 = 0; define
17 R0 = B [ P0 ] (Z); define
20 R0 = CC; define
22 R0 = B [ P0 ] (Z); define
25 R0 = 0; define
28 R0 = CC; define
30 R0 = B [ P0 ] (Z); define
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| H A D | dsp_d1.s | 14 R0 = [ I0 ++ M1 ]; define
18 R0 = [ I0 ++ M1 ]; define
23 R0 = [ I0 ++ M1 ]; define
33 R0 = [ I0 ++ M1 ]; define
37 R0 = [ I0 ++ M1 ]; define
41 R0 = [ I0 ++ M1 ]; define
45 R0 = [ I0 ++ M1 ]; define
49 R0 = [ I0 ++ M1 ]; define
58 R0 = [ I0 ++ ]; define
62 R0 = [ I0 ++ ]; define
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| H A D | a1.s | 7 R0 = 63; define
9 R0 = -64; define
12 R0 = P0; DBGA ( R0.L , 63 ); define
14 R0 = P0; DBGA ( R0.L , 0xffc0 ); define
24 R0 = P0; DBGA ( R0.L , 0x2222 ); define
27 R0 = P0; DBGA ( R0.H , 0x2222 ); define
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| H A D | se_loop_mv2lb_stall.S | 116 R0 = 0; define
121 R0 = -1; define
368 R0 = [ P2 ++ ]; define
382 R0 = [ P2 ++ ]; define
397 R0 = [ P2 ++ ]; define
413 R0 = [ P2 ++ ]; define
430 R0 = [ P2 ++ ]; define
450 R0 = [ P2 ++ ]; define
465 R0 = [ P2 ++ ]; define
479 R0 = [ P2 ++ ]; define
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| H A D | se_loop_mv2lc_stall.S | 116 R0 = 0; define
121 R0 = -1; define
372 R0 = [ P2 ++ ]; define
386 R0 = [ P2 ++ ]; define
401 R0 = [ P2 ++ ]; define
417 R0 = [ P2 ++ ]; define
434 R0 = [ P2 ++ ]; define
452 R0 = [ P2 ++ ]; define
467 R0 = [ P2 ++ ]; define
481 R0 = [ P2 ++ ]; define
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| H A D | se_regmv_usp_sysreg.S | 26 R0 = 0; define
32 R0 = 0x59c4 (Z); define
38 R0 = 0xd4a4 (Z); define
45 R0 = 0x2bca (Z); define
52 R0 = 0x6d4a (Z); define
59 R0 = 0x6b18 (Z); define
66 R0 = 0x62da (Z); define
73 R0 = 0x7c60 (Z); define
80 R0 = 0x182 (Z); define
87 R0 = 0xd5a2 (Z); define
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| H A D | l0.s | 8 R0 = [ P0 ++ ]; define
28 R0 = W [ P0 ++ ] (Z); define
46 R0 = B [ P0 ++ ] (Z); define
55 R0 = B [ P0 ++ ] (X); define
61 R0 = W [ P0 ++ ] (X); define
69 R0 = P1; define
74 R0 = P1; define
80 R0 = B [ P5 ++ ] (X); define
84 R0 = B [ P5 ++ ] (X); define
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| H A D | se_excpt_ssstep.S | 107 R0 = 0; define
109 R0 = -1; // Change this to mask interrupts (*) define
114 R0 = 0 (Z); define
131 R0 = 1; define
172 R0 = 0; define
173 R0 = 0; define
174 R0 = 0; define
175 R0 = 0; define
176 R0 = 0; define
178 R0 = 0; define
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| H A D | lmu_excpt_prot0.S | 31 R0 = 0; define
142 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
175 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
201 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
213 R0 = [ P1 ]; define
224 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
248 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; define
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| H A D | a20.S | 20 R0 = R0 +|- R0; define
25 R0 = 0; define
33 R0 = ABS R1; define
42 R0 = ABS R1; define
48 R0 = 0; define
53 R0 = R1 +|+ R1 (CO); define
63 R0 = PACK( R0.H , R1.L ); define
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| H A D | up0.s | 7 R0 = 1; define
15 R0 = A0.x; define
19 R0 = P0; define
22 R0 = 45; define
29 R0 = 0x0333 (X); define
34 R0 = [ P0 ]; define
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| H A D | c_mode_user_superivsor.S | 100 R0 = 0; define
102 R0 = -1; // Change this to mask interrupts (*) define
107 R0 = 0 (Z); define
176 R0 = I0; define
211 R0 = RETN; define
221 R0 = RETX; define
230 R0 = RETI; define
239 R0 = RETI; define
245 R0 = RETI; define
254 R0 = RETI; define
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