| /llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1738 EVT PartVT = VT; getVectorTypeBreakdown() local
1850 MVT PartVT = GetReturnInfo() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 170 getCopyFromParts(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,const Value * V,SDValue InChain,std::optional<CallingConv::ID> CC=std::nullopt,std::optional<ISD::NodeType> AssertOp=std::nullopt) getCopyFromParts() argument
343 getCopyFromPartsVector(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,const Value * V,SDValue InChain,std::optional<CallingConv::ID> CallConv) getCopyFromPartsVector() argument
508 getCopyToParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,const Value * V,std::optional<CallingConv::ID> CallConv=std::nullopt,ISD::NodeType ExtendKind=ISD::ANY_EXTEND) getCopyToParts() argument
644 widenVectorToPartType(SelectionDAG & DAG,SDValue Val,const SDLoc & DL,EVT PartVT) widenVectorToPartType() argument
692 getCopyToPartsVector(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,const Value * V,std::optional<CallingConv::ID> CallConv) getCopyToPartsVector() argument
2260 MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT); visitRet() local
10960 MVT PartVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), LowerCallTo() local
11648 MVT PartVT = TLI->getRegisterTypeForCallingConv(*CurDAG->getContext(), LowerArguments() local
[all...] |
| H A D | LegalizeVectorTypes.cpp | 5552 EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT, WidenVecRes_EXTRACT_SUBVECTOR() local
6156 EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT, WidenVecRes_VECTOR_REVERSE() local
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| H A D | LegalizeDAG.cpp | 1470 EVT PartVT = Part.getValueType(); ExpandInsertToVectorThroughStack() local
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| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1582 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument
1595 joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,std::optional<CallingConv::ID> CC) const joinRegisterPartsIntoValue() argument
1950 MVT PartVT = getRegisterTypeForCallingConv(Ctx, CLI.CallConv, OrigArgVT); LowerCall() local
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 4455 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) splitValueIntoRegisterParts() argument
4480 joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,std::optional<CallingConv::ID> CC) joinRegisterPartsIntoValue() argument
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| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4274 EVT PartVT = PartValue.getValueType(); LowerCall() local
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| /llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 3143 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 798 MVT PartVT = MVT::getVectorVT(VecTy.getVectorElementType(), OpsPerWord); in buildHvxVectorReg() local
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2335 MVT PartVT = TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT); getRegisterTypeForCallingConv() local
19964 EVT PartVT = PartValue.getValueType(); LowerCall() local
21415 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument
21470 joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,std::optional<CallingConv::ID> CC) const joinRegisterPartsIntoValue() argument
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4477 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument
4493 joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,std::optional<CallingConv::ID> CC) const joinRegisterPartsIntoValue() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 18476 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument
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