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Searched defs:PartTy (Results 1 – 5 of 5) sorted by relevance

/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp527 buildCopyToRegs(MachineIRBuilder & B,ArrayRef<Register> DstRegs,Register SrcReg,LLT SrcTy,LLT PartTy,unsigned ExtendOp=TargetOpcode::G_ANYEXT) buildCopyToRegs() argument
1006 Type *PartTy = EVT(RegVT).getTypeForEVT(Context); getReturnInfo() local
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H A DLegalizerHelper.cpp162 insertParts(Register DstReg,LLT ResultTy,LLT PartTy,ArrayRef<Register> PartRegs,LLT LeftoverTy,ArrayRef<Register> LeftoverRegs) insertParts() argument
4381 LLT PartTy = MRI.getType(VecParts[PartIdx]); fewerElementsVectorExtractInsertVectorElt() local
4459 __anon2d1bd0d20102(LLT PartTy, SmallVectorImpl<Register> &ValRegs, unsigned NumParts, unsigned Offset) reduceLoadStoreWidth() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DSROA.cpp4484 auto *PartTy = Type::getIntNTy(LI->getContext(), PartSize * 8); presplitLoadsAndStores() local
4620 auto *PartTy = Type::getIntNTy(Ty->getContext(), PartSize * 8); presplitLoadsAndStores() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp897 LLT PartTy = LLT::scalar(PartSize); in executeInWaterfallLoop() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3181 MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign) LowerUnalignedLoad() local