| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 458 EVT OutVT = N->getValueType(0); PromoteIntRes_BITCAST() local
5670 EVT OutVT = V0.getValueType(); PromoteIntRes_VECTOR_SPLICE() local
5690 EVT OutVT = N->getValueType(0); PromoteIntRes_EXTRACT_SUBVECTOR() local
5772 EVT OutVT = N->getValueType(0); PromoteIntRes_INSERT_SUBVECTOR() local
5796 EVT OutVT = V0.getValueType(); PromoteIntRes_VECTOR_REVERSE() local
5810 EVT OutVT = V0.getValueType(); PromoteIntRes_VECTOR_SHUFFLE() local
5816 EVT OutVT = N->getValueType(0); PromoteIntRes_BUILD_VECTOR() local
5856 EVT OutVT = N->getValueType(0); PromoteIntRes_ScalarOp() local
5868 EVT OutVT = N->getValueType(0); PromoteIntRes_STEP_VECTOR() local
5880 EVT OutVT = N->getValueType(0); PromoteIntRes_CONCAT_VECTORS() local
5983 EVT OutVT = N->getValueType(0); PromoteIntRes_INSERT_VECTOR_ELT() local
6049 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(), PromoteIntOp_EXTRACT_SUBVECTOR() local
[all...] |
| H A D | LegalizeTypesGeneric.cpp | 41 EVT OutVT = N->getValueType(0); in ExpandRes_BITCAST() local
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| H A D | LegalizeVectorTypes.cpp | 3354 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), SplitVecOp_UnaryOp() local
3976 EVT OutVT = N->getValueType(0); SplitVecOp_TruncateHelper() local
4119 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), SplitVecOp_FP_ROUND() local
[all...] |
| H A D | DAGCombiner.cpp | 25148 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), OutSVT, NumElts / Scale); canCombineShuffleToExtendVectorInreg() local
25192 std::optional<EVT> OutVT = canCombineShuffleToExtendVectorInreg( combineShuffleToAnyExtendVectorInreg() local
25313 std::optional<EVT> OutVT = canCombineShuffleToExtendVectorInreg( combineShuffleToZeroExtendVectorInReg() local
27973 BuildLogBase2(SDValue V,const SDLoc & DL,bool KnownNonZero,bool InexpensiveOnly,std::optional<EVT> OutVT) BuildLogBase2() argument
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| H A D | SelectionDAGBuilder.cpp | 12375 EVT OutVT = visitVectorDeinterleave() local
12409 EVT OutVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); visitVectorInterleave() local
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| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 5184 MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8), getPermuteNode() local
5564 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(OutBits), insertUnpackIfPrepared() local
5969 EVT OutVT = Op.getValueType(); lowerSIGN_EXTEND_VECTOR_INREG() local
5975 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits), lowerSIGN_EXTEND_VECTOR_INREG() local
5988 EVT OutVT = Op.getValueType(); lowerZERO_EXTEND_VECTOR_INREG() local
6793 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(ElemBytes * 16), combineMERGE() local
7451 EVT OutVT = N->getValueType(0); combineINT_TO_FP() local
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| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2744 EVT InVT = MVT::i16, OutVT = MVT::i8; truncateVectorWithNARROW() local
2784 EVT OutVT = N->getValueType(0); performTruncateCombine() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 20855 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); getPTest() local
24484 SDValue OutVT = DAG.getValueType(RetVT); performGatherLoadCombine() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8793 EVT OutVT = Op.getValueType(); LowerINT_TO_FP() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 20356 EVT InVT = MVT::i16, OutVT = MVT::i8; truncateVectorWithPACK() local
[all...] |