| /llvm-project/clang-tools-extra/test/clang-tidy/checkers/performance/ |
| H A D | inefficient-algorithm.cpp | 62 FwIt lower_bound(FwIt, FwIt end, const K &, Ord) { return end; } in lower_bound() argument
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| /llvm-project/clang/lib/Sema/ |
| H A D | SemaAMDGPU.cpp | 77 auto Ord = ArgResult.Val.getInt().getZExtValue(); CheckAMDGCNBuiltinFunctionCall() local
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| H A D | SemaOverload.cpp | 12247 if (int Ord = CompareConversions(*L, *R)) operator ()() local
12301 if (int Ord = CompareConversions(*L, *R)) operator ()() local
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | LocalStackSlotAllocation.cpp | 62 FrameRef(MachineInstr *I, int64_t Offset, int Idx, unsigned Ord) : in FrameRef() argument
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| /llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVUtils.cpp | 236 getMemSemantics(AtomicOrdering Ord) getMemSemantics() argument
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| H A D | SPIRVInstructionSelector.cpp | 720 getScope(SyncScope::ID Ord,SPIRVMachineModuleInfo * MMI) getScope() argument
966 SyncScope::ID Ord = SyncScope::ID(I.getOperand(1).getImm()); selectFence() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 518 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister() local
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| H A D | AArch64FastISel.cpp | 2192 AtomicOrdering Ord = SI->getOrdering(); selectStore() local
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| /llvm-project/llvm/lib/ObjectYAML/ |
| H A D | CodeViewYAMLSymbols.cpp | 195 ThunkOrdinal &Ord) { in enumeration() argument
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| /llvm-project/llvm/bindings/ocaml/llvm/ |
| H A D | llvm.ml | 167 | Ord Constructor
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| H A D | llvm.mli | 192 | Ord (** Ordered (no operand is NaN) *) Constructor
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| H A D | llvm_ocaml.c | 2405 llvm_build_atomicrmw_native(value BinOp,value Ptr,value Val,value Ord,value ST,value Name,value B) llvm_build_atomicrmw_native() argument
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2165 emitLoadLinked(IRBuilderBase & Builder,Type * ValueTy,Value * Addr,AtomicOrdering Ord) emitLoadLinked() argument
2172 emitStoreConditional(IRBuilderBase & Builder,Value * Val,Value * Addr,AtomicOrdering Ord) emitStoreConditional() argument
2184 emitMaskedAtomicRMWIntrinsic(IRBuilderBase & Builder,AtomicRMWInst * AI,Value * AlignedAddr,Value * Incr,Value * Mask,Value * ShiftAmt,AtomicOrdering Ord) emitMaskedAtomicRMWIntrinsic() argument
2218 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) emitMaskedAtomicCmpXchgIntrinsic() argument
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| /llvm-project/llvm/tools/llvm-c-test/ |
| H A D | echo.cpp | 781 LLVMAtomicOrdering Ord = LLVMGetOrdering(Src); CloneInstruction() local
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| /llvm-project/llvm/lib/ProfileData/Coverage/ |
| H A D | CoverageMapping.cpp | 259 unsigned Ord = 0; TVIdxBuilder() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 414 const RegisterOrdering &Ord; member in __anon494378ab0311::OrderedRegisterList
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4297 AtomicOrdering Ord = LowerATOMIC_FENCE() local
[all...] |