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Searched defs:Op3 (Results 1 – 25 of 26) sorted by relevance

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/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp235 unsigned &Op3) { in Decode3OpInstruction()
514 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
527 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
540 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
553 unsigned Op1, Op2, Op3; in Decode2RUSBitpInstruction() local
566 unsigned Op1, Op2, Op3; in DecodeL3RInstruction() local
580 unsigned Op1, Op2, Op3; in DecodeL3RSrcDstInstruction() local
595 unsigned Op1, Op2, Op3; in DecodeL2RUSInstruction() local
609 unsigned Op1, Op2, Op3; in DecodeL2RUSBitpInstruction() local
623 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
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/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h96 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
53 EmitTargetCodeForMemcpy(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Op1,SDValue Op2,SDValue Op3,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) EmitTargetCodeForMemcpy() argument
69 EmitTargetCodeForMemmove(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Op1,SDValue Op2,SDValue Op3,Align Alignment,bool isVolatile,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) EmitTargetCodeForMemmove() argument
83 EmitTargetCodeForMemset(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Op1,SDValue Op2,SDValue Op3,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo) EmitTargetCodeForMemset() argument
/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.cpp38 EmitTargetCodeForMemmove(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Op1,SDValue Op2,SDValue Op3,Align Alignment,bool IsVolatile,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForMemmove() argument
/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h110 const MachineOperand &Op3 = MI->getOperand(Operand + 3); in getAddressFromInstr() local
H A DX86FastISel.cpp4038 fastEmitInst_rrrr(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,unsigned Op1,unsigned Op2,unsigned Op3) fastEmitInst_rrrr() argument
H A DX86ISelDAGToDAG.cpp6590 SDValue Op0, Op1, Op2, Op3, Op4; SelectInlineAsmMemoryOperand() local
H A DX86InstrInfo.cpp2059 unsigned Op1 = 1, Op2 = 2, Op3 = 3; getThreeSrcCommuteCase() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankCombiner.cpp332 return Op3->getOperand(1).getFPImm()->isExactlyValue(0.0); in matchFPMed3ToClamp() local
/llvm-project/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp293 BPFOperand &Op3 = (BPFOperand &)*Operands[3]; PreMatchCheck() local
/llvm-project/llvm/unittests/Transforms/Vectorize/
H A DVPlanTest.cpp930 VPValue *Op3 = Plan.getOrAddLiveIn(ConstantInt::get(Int32, 3)); in TEST() local
1086 VPValue Op3; TEST() local
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1344 const MachineOperand &Op3 = MI.getOperand(3); expandPostRAPseudo() local
1368 const MachineOperand &Op3 = MI.getOperand(3); expandPostRAPseudo() local
1401 MachineOperand &Op3 = MI.getOperand(3); expandPostRAPseudo() local
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H A DHexagonSplitDouble.cpp903 MachineOperand &Op3 = MI->getOperand(3); in splitAslOr() local
/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp6221 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); MatchAndEmitInstruction() local
6307 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); MatchAndEmitInstruction() local
6371 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); MatchAndEmitInstruction() local
6430 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); MatchAndEmitInstruction() local
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/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp233 emitRRRX(unsigned Opcode,unsigned Reg0,unsigned Reg1,unsigned Reg2,MCOperand Op3,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRRX() argument
/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp233 fastEmitInst_riir(uint64_t inst,const TargetRegisterClass * RC,unsigned Op0,uint64_t imm1,uint64_t imm2,unsigned Op3) fastEmitInst_riir() argument
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp10466 UpdateNodeOperands(SDNode * N,SDValue Op1,SDValue Op2,SDValue Op3) UpdateNodeOperands() argument
10473 UpdateNodeOperands(SDNode * N,SDValue Op1,SDValue Op2,SDValue Op3,SDValue Op4) UpdateNodeOperands() argument
10480 UpdateNodeOperands(SDNode * N,SDValue Op1,SDValue Op2,SDValue Op3,SDValue Op4,SDValue Op5) UpdateNodeOperands() argument
10574 SelectNodeTo(SDNode * N,unsigned MachineOpc,EVT VT,SDValue Op1,SDValue Op2,SDValue Op3) SelectNodeTo() argument
10781 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT,SDValue Op1,SDValue Op2,SDValue Op3) getMachineNode() argument
10803 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT1,EVT VT2,SDValue Op1,SDValue Op2,SDValue Op3) getMachineNode() argument
10827 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT1,EVT VT2,EVT VT3,SDValue Op1,SDValue Op2,SDValue Op3) getMachineNode() argument
[all...]
H A DSelectionDAGBuilder.cpp6533 SDValue MC = DAG.getMemcpy(Root, sdl, Op1, Op2, Op3, Alignment, isVol, in visitIntrinsicCall() local
6457 SDValue Op3 = getValue(I.getArgOperand(2)); visitIntrinsicCall() local
6499 SDValue Op3 = getValue(I.getArgOperand(2)); visitIntrinsicCall() local
7207 SDValue Op3 = getValue(I.getArgOperand(2)); visitIntrinsicCall() local
7218 SDValue Op3 = getValue(I.getArgOperand(2)); visitIntrinsicCall() local
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H A DLegalizeFloatTypes.cpp3177 SDValue Op3 = GetSoftPromotedHalf(N->getOperand(3)); SoftPromoteHalfRes_SELECT_CC() local
H A DLegalizeIntegerTypes.cpp428 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); PromoteIntRes_AtomicCmpSwap() local
/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp106 const MCOperand &Op3 = MI->getOperand(3); printInst() local
/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp17338 Value *Op3 = EmitScalarExpr(E->getArg(3)); EmitPPCBuiltinExpr() local
17983 Value *Op3 = EmitScalarExpr(E->getArg(3)); EmitPPCBuiltinExpr() local
17991 Value *Op3 = EmitScalarExpr(E->getArg(3)); EmitPPCBuiltinExpr() local
17999 Value *Op3 = EmitScalarExpr(E->getArg(3)); EmitPPCBuiltinExpr() local
18007 Value *Op3 = EmitScalarExpr(E->getArg(3)); EmitPPCBuiltinExpr() local
18015 Value *Op3 = EmitScalarExpr(E->getArg(3)); EmitPPCBuiltinExpr() local
18023 Value *Op3 = EmitScalarExpr(E->getArg(3)); EmitPPCBuiltinExpr() local
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/llvm-project/llvm/lib/Analysis/
H A DConstantFolding.cpp3104 if (const auto *Op3 = dyn_cast<ConstantFP>(Operands[2])) { ConstantFoldScalarCall3() local
/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp6766 const auto &Op3 = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]); tryConvertingToTwoOperandForm() local
6937 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[IdX + 1]); fixupGNULDRDAlias() local
7017 const MCParsedAsmOperand &Op3 = *Operands[MnemonicOpsEndInd + 2]; CDEConvertDualRegOperand() local
/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h1635 T2 Op3; global() member
[all...]
/llvm-project/llvm/lib/IR/
H A DVerifier.cpp5913 auto *Op3 = cast<ConstantInt>(Call.getArgOperand(2)); visitIntrinsicCall() local

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