| /llvm-project/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 216 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction()
234 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction()
322 unsigned Op1, Op2; in Decode2RInstruction() local
335 unsigned Op1, Op2; in Decode2RImmInstruction() local
348 unsigned Op1, Op2; in DecodeR2RInstruction() local
361 unsigned Op1, Op2; in Decode2RSrcDstInstruction() local
375 unsigned Op1, Op2; in DecodeRUSInstruction() local
388 unsigned Op1, Op2; in DecodeRUSBitpInstruction() local
401 unsigned Op1, Op2; in DecodeRUSSrcDstBitpInstruction() local
486 unsigned Op1, Op2; in DecodeL2RInstruction() local
[all …]
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGTargetInfo.h | 96 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
53 EmitTargetCodeForMemcpy(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Op1,SDValue Op2,SDValue Op3,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) EmitTargetCodeForMemcpy() argument
69 EmitTargetCodeForMemmove(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Op1,SDValue Op2,SDValue Op3,Align Alignment,bool isVolatile,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) EmitTargetCodeForMemmove() argument
83 EmitTargetCodeForMemset(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Op1,SDValue Op2,SDValue Op3,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo) EmitTargetCodeForMemset() argument
133 EmitTargetCodeForStrcmp(SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Op1,SDValue Op2,MachinePointerInfo Op1PtrInfo,MachinePointerInfo Op2PtrInfo) EmitTargetCodeForStrcmp() argument
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| /llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCCodeEmitter.cpp | 143 const MCOperand Op2 = Inst.getOperand(2); adjustPqBits() local
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1); getRiMemoryOpValue() local
222 const MCOperand Op2 = Inst.getOperand(OpNo + 1); getRrMemoryOpValue() local
261 const MCOperand Op2 = Inst.getOperand(OpNo + 1); getSplsOpValue() local
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandImm.h | 25 uint64_t Op2; member
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| /llvm-project/llvm/unittests/Transforms/Vectorize/ |
| H A D | VPlanTest.cpp | 929 VPValue *Op2 = Plan.getOrAddLiveIn(ConstantInt::get(Int32, 2)); in TEST() local
866 VPValue Op2; TEST() local
881 VPValue Op2; TEST() local
901 VPValue Op2; TEST() local
957 VPValue Op2; TEST() local
1010 VPValue Op2; TEST() local
1068 VPValue Op2; TEST() local
1085 VPValue Op2; TEST() local
1103 VPValue Op2; TEST() local
1168 VPValue Op2; TEST() local
1191 VPValue Op2; TEST() local
1207 VPValue Op2; TEST() local
1219 VPValue Op2; TEST() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 253 const MachineMemOperand &Op2, in alias()
279 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias() local
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| /llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.cpp | 158 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; parseGenericRegister() local
176 uint32_t Op2 = Bits & 0x7; genericRegisterString() local
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| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 169 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand()
293 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local
|
| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblySelectionDAGInfo.cpp | 37 EmitTargetCodeForMemmove(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Op1,SDValue Op2,SDValue Op3,Align Alignment,bool IsVolatile,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) const EmitTargetCodeForMemmove() argument
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| H A D | WebAssemblyPeephole.cpp | 141 const auto &Op2 = MI.getOperand(2); in runOnMachineFunction() local
|
| /llvm-project/llvm/lib/Target/BPF/MCTargetDesc/ |
| H A D | BPFMCCodeEmitter.cpp | 166 assert(Op2.isImm() && "Second operand is not immediate."); in getMemoryOpValue() local
|
| /llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 309 auto Op2 = N->getOperand(2); in selectAddCarry() local
352 auto Op2 = N->getOperand(2); in selectSubCarry() local
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| /llvm-project/llvm/unittests/CodeGen/ |
| H A D | SelectionDAGPatternMatchTest.cpp | 109 SDValue Op2 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 2, VInt32VT); in TEST_F() local
129 SDValue Op2 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 3, Float32VT); TEST_F() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 344 const MachineOperand &Op2 = MI->getOperand(2); in profit() local
726 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
778 MachineOperand &Op2 in splitShift() local
902 MachineOperand &Op2 = MI->getOperand(2); splitAslOr() local
[all...] |
| H A D | HexagonNewValueJump.cpp | 250 const MachineOperand &Op2 = MI.getOperand(2); in canCompareBeNewValueJump() local
|
| /llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcInstPrinter.cpp | 153 const MCOperand &Op2 = MI->getOperand(opNum + 1); printMemOperand() local
|
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 107 const MachineOperand &Op2 = MI->getOperand(Operand + 2); in getAddressFromInstr() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMacroFusion.cpp | 73 const MachineOperand &Op2 = SecondMI.getOperand(SecondMIOpIndex); in matchingRegOps() local
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| H A D | PPCExpandISEL.cpp | |
| H A D | PPCBranchCoalescing.cpp | 341 const MachineOperand &Op2 = OpList2[i]; in identicalOperands() local
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| /llvm-project/llvm/lib/IR/ |
| H A D | ProfileSummary.cpp | 166 ConstantAsMetadata *Op2 = in getSummaryFromMD() local
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| H A D | DIExpressionOptimizer.cpp | 165 auto Op2 = Cursor.peekNext(); optimizeDwarfOperations() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreEmitPeephole.cpp | 117 MachineOperand &Op2 = A->getOperand(2); optimizeVccBranch() local
[all...] |
| /llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 132 const MachineOperand *Op2 = &Inst->getOperand(2); in checkADDrr() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 1142 SDValue Op2 = Node->getOperand(2); ExpandSELECT() local
1409 SDValue Op2 = Node->getOperand(2); ExpandVSELECT() local
1459 SDValue Op2 = Node->getOperand(2); ExpandVP_SELECT() local
1492 SDValue Op2 = Node->getOperand(2); ExpandVP_MERGE() local
[all...] |