Lines Matching defs:Op2

344       const MachineOperand &Op2 = MI->getOperand(2);
346       int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0;
726   MachineOperand &Op2 = MI->getOperand(2);
743   if (!Op2.isReg()) {
745       .add(Op2);
748       .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
778   MachineOperand &Op2 = MI->getOperand(2);
779   assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
780   int64_t Sh64 = Op2.getImm();
902   MachineOperand &Op2 = MI->getOperand(2);
904   assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
918   unsigned RS2 = getRegState(Op2);
924   // Op0 = S2_asl_i_p_or Op1, Op2, Op3
925   // means:  Op0 = or (Op1, asl(Op2, Op3))
942       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
945       .addReg(Op2.getReg(), RS2, HiSR);
949       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
953       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
962       .addReg(Op2.getReg(), RS2, HiSR)
973       .addReg(Op2.getReg(), RS2, LoSR);
984       .addReg(Op2.getReg(), RS2, LoSR)