| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 156 bool OffsetIsScalable; runOnMachineFunction() local
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| H A D | AArch64InstrInfo.cpp | 2701 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, in getAddrModeFromMemoryOp() local
2676 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,unsigned & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
3470 getMemOperandWithOffsetWidth(const MachineInstr & LdSt,const MachineOperand * & BaseOp,int64_t & Offset,bool & OffsetIsScalable,TypeSize & Width,const TargetRegisterInfo * TRI) const getMemOperandWithOffsetWidth() argument
8403 bool OffsetIsScalable; getOutliningCandidateInfo() local
8936 bool OffsetIsScalable; fixupPostOutline() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 796 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,unsigned & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 1366 getMemOperandWithOffset(const MachineInstr & MI,const MachineOperand * & BaseOp,int64_t & Offset,bool & OffsetIsScalable,const TargetRegisterInfo * TRI) const getMemOperandWithOffset() argument
1495 bool OffsetIsScalable; describeLoadedValue() local
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| H A D | MachineSink.cpp | 1308 bool OffsetIsScalable; SinkingPreventsImplicitNullCheck() local
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| H A D | MachineScheduler.cpp | 1701 bool OffsetIsScalable; global() member
1910 bool OffsetIsScalable; collectMemOpRecords() local
[all...] |
| H A D | ModuloSchedule.cpp | 924 bool OffsetIsScalable; computeDelta() local
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| H A D | MachinePipeliner.cpp | 2516 bool OffsetIsScalable; computeDelta() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 1920 bool OffsetIsScalable; schedule() local
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| H A D | SIInstrInfo.cpp | 363 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,unsigned & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1449 getMemOperandsWithOffsetWidth(const MachineInstr & MI,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,unsigned & Width,const TargetRegisterInfo * TRI) getMemOperandsWithOffsetWidth() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 2205 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,unsigned & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 3045 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,unsigned & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2823 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,unsigned & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 4511 getMemOperandsWithOffsetWidth(const MachineInstr & MemOp,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,unsigned & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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