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Searched defs:NewOpc (Results 1 – 25 of 69) sorted by relevance

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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupInstTuning.cpp107 bool ReplaceInTie = true) -> bool { in processInstruction()
133 auto ProcessVPERMILPDri = [&](unsigned NewOpc) -> bool { in processInstruction()
148 auto ProcessVPERMILPSri = [&](unsigned NewOpc) -> bool { in processInstruction()
162 auto ProcessVPERMILPSmi = [&](unsigned NewOpc) -> bool { in processInstruction()
186 auto ProcessUNPCK = [&](unsigned NewOpc, unsigned MaskImm) -> bool { in processInstruction()
195 auto ProcessUNPCKToIntDomain = [&](unsigned NewOpc) -> bool { in processInstruction()
207 unsigned NewOpc) -> bool { in processInstruction()
213 unsigned NewOpc) -> bool { in processInstruction()
223 auto ProcessUNPCKPS = [&](unsigned NewOpc) -> bool { in processInstruction()
H A DX86FixupLEAs.cpp810 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
848 unsigned NewOpc = in processInstrForSlow3OpLEA() local
854 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); in processInstrForSlow3OpLEA() local
882 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
905 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
H A DX86CompressEVEX.cpp125 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && in performCustomAdjustments() argument
56 uint16_t NewOpc; global() member
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H A DX86ISelDAGToDAG.cpp1124 unsigned NewOpc; PreprocessISelDAG() local
1157 unsigned NewOpc; PreprocessISelDAG() local
1179 unsigned NewOpc; PreprocessISelDAG() local
1574 unsigned NewOpc; PostprocessISelDAG() local
1618 unsigned NewOpc; PostprocessISelDAG() local
3568 unsigned NewOpc = SelectOpcode(X86::NEG64m, X86::NEG32m, X86::NEG16m, foldLoadStoreIntoMemOperand() local
3583 unsigned NewOpc = foldLoadStoreIntoMemOperand() local
3653 unsigned NewOpc = SelectRegOpcode(Opc); foldLoadStoreIntoMemOperand() local
4103 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; matchBEXTRFromAndImm() local
4121 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; matchBEXTRFromAndImm() local
4145 unsigned NewOpc = NVT == MVT::i64 ? X86::SHR64ri : X86::SHR32ri; matchBEXTRFromAndImm() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86EncodingOptimization.cpp25 unsigned NewOpc = 0; in optimizeInstFromVEX3ToVEX2() local
105 unsigned NewOpc; in optimizeShiftRotateWithImmediateOne() local
254 unsigned NewOpc; optimizeVPCMPWithImmediateOneOrSix() local
267 unsigned NewOpc; optimizeMOVSX() local
291 unsigned NewOpc; optimizeINCDEC() local
319 unsigned NewOpc; optimizeMOV() local
374 unsigned NewOpc; optimizeToFixedRegisterForm() local
451 unsigned NewOpc; optimizeToShortImmediateForm() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFoldMasks.cpp
H A DRISCVExpandPseudoInsts.cpp205 unsigned NewOpc; in expandCCOp() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CondBrTuning.cpp98 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode()); in convertToFlagSetting() local
H A DAArch64AdvSIMDScalarPass.cpp292 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp879 unsigned NewOpc = ExpandMQQPRLoadStore() local
2130 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq; ExpandMI() local
2140 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq; ExpandMI() local
2150 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq; ExpandMI() local
2424 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; ExpandMI() local
2466 unsigned NewOpc; ExpandMI() local
2760 unsigned NewOpc = ARM::VLDMDIA; ExpandMI() local
2791 unsigned NewOpc = ARM::VSTMDIA; ExpandMI() local
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H A DARMLoadStoreOptimizer.cpp1348 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); MergeBaseUpdateLSMultiple() local
1500 unsigned NewOpc; MergeBaseUpdateLoadStore() local
1637 unsigned NewOpc; MergeBaseUpdateLSDouble() local
1734 InsertLDR_STR(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,int Offset,bool isDef,unsigned NewOpc,unsigned Reg,bool RegDeadKill,bool RegUndef,unsigned BaseReg,bool BaseKill,bool BaseUndef,ARMCC::CondCodes Pred,unsigned PredReg,const TargetInstrInfo * TII,MachineInstr * MI) InsertLDR_STR() argument
1806 unsigned NewOpc = (isLd) FixInvalidRegPairOp() local
1830 unsigned NewOpc = (isLd) FixInvalidRegPairOp() local
2058 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); MergeReturnIntoLDM() local
2254 CanFormLdStDWord(MachineInstr * Op0,MachineInstr * Op1,DebugLoc & dl,unsigned & NewOpc,Register & FirstReg,Register & SecondReg,Register & BaseReg,int & Offset,Register & PredReg,ARMCC::CondCodes & Pred,bool & isT2) CanFormLdStDWord() argument
2418 unsigned NewOpc = 0; RescheduleOps() local
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H A DThumb2InstrInfo.cpp590 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 rewriteT2FrameIndex() local
623 unsigned NewOpc = Opcode; rewriteT2FrameIndex() local
H A DARMConstantIslandPass.cpp1845 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1896 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1930 unsigned NewOpc = 0; optimizeThumb2Branches() member
1944 unsigned NewOpc = 0; optimizeThumb2Branches() local
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H A DARMInstructionSelector.cpp899 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize); select() local
1095 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); select() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp204 unsigned NewOpc = getNonFlagSettingVariant(II.getOpcode()); optimizeNZCVDefs() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp579 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign()); selectLoadStoreOp() local
621 unsigned NewOpc = getLeaOP(Ty, STI); selectFrameIndexOrGep() local
672 unsigned NewOpc = getLeaOP(Ty, STI); selectGlobalValue() local
704 unsigned NewOpc; selectConstant() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp251 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRDFOpt.cpp226 unsigned OpNum, NewOpc; rewrite() local
H A DHexagonGenPredicate.cpp387 unsigned NewOpc = getPredForm(Opc); in convertToPredForm() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp475 const unsigned NewOpc = TryAK ? AMDGPU::S_FMAAK_F32 : AMDGPU::S_FMAMK_F32; tryAddToFoldList() local
512 unsigned NewOpc = macToMad(Opc); tryAddToFoldList() local
821 unsigned NewOpc = AMDGPU::getFlatScratchInstSSfromSV(Opc); foldOperand() local
H A DSIInstrInfo.cpp1149 int NewOpc; commuteOpcode() local
3409 unsigned NewOpc = isVGPRCopy ? Is64Bit ? AMDGPU::V_MOV_B64_PSEUDO FoldImmediate() local
3502 unsigned NewOpc = FoldImmediate() local
3581 unsigned NewOpc = FoldImmediate() local
3789 unsigned NewOpc = AMDGPU::mapWMMA2AddrTo3AddrOpcode(MI.getOpcode()); convertToThreeAddress() local
3892 unsigned NewOpc = convertToThreeAddress() local
3910 unsigned NewOpc = convertToThreeAddress() local
3958 unsigned NewOpc = IsFMA ? IsF16 ? AMDGPU::V_FMA_F16_gfx9_e64 convertToThreeAddress() local
6010 int NewOpc = AMDGPU::getGlobalVaddrOp(Opc); moveFlatAddrToVGPR() local
7400 unsigned NewOpc = Opc == AMDGPU::S_ADD_I32 ? moveScalarAddSub() local
7857 unsigned NewOpc = Opc == AMDGPU::S_MUL_U64_U32_PSEUDO splitScalarSMulPseudo() local
9742 unsigned NewOpc = (SrcSize == 32) ? IsReversedCC ? AMDGPU::S_BITCMP0_B32 optimizeCompareInstr() local
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H A DAMDGPUPostLegalizerCombiner.cpp368 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; applyCvtF32UByteN() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp740 const unsigned NewOpc = selectLoadStoreOp( in select() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp685 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc() argument
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H A DMipsBranchExpansion.cpp342 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch() local

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