Lines Matching defs:NewOpc

1349   unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
1350   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1501   unsigned NewOpc;
1503     NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1505     NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1511     NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1513         (!isAM5 && !isLegalAddressImm(NewOpc, Offset, TII))) {
1514       NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1515       if (isAM5 || !isLegalAddressImm(NewOpc, Offset, TII))
1531     auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1544       if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
1546             BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1558             BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1571           BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1585     if (isAM2 && NewOpc == ARM::STR_POST_IMM) {
1588       auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1599       auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1638   unsigned NewOpc;
1640     NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE;
1645     NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST;
1646     if (!isLegalAddressImm(NewOpc, Offset, TII))
1653   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
1654   if (NewOpc == ARM::t2LDRD_PRE || NewOpc == ARM::t2LDRD_POST) {
1657     assert(NewOpc == ARM::t2STRD_PRE || NewOpc == ARM::t2STRD_POST);
1663          TII->get(NewOpc).getNumOperands() == 7 &&
1735                           bool isDef, unsigned NewOpc, unsigned Reg,
1742                                       TII->get(NewOpc))
1751                                       TII->get(NewOpc))
1807     unsigned NewOpc = (isLd)
1811       BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1819       BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1831     unsigned NewOpc = (isLd)
1845       InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,
1859       InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,
2059       unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET);
2062       PrevMI.setDesc(TII->get(NewOpc));
2171                           unsigned &NewOpc, Register &EvenReg, Register &OddReg,
2256     MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc,
2267     NewOpc = ARM::LDRD;
2269     NewOpc = ARM::STRD;
2271     NewOpc = ARM::t2LDRDi8;
2275     NewOpc = ARM::t2STRDi8;
2420         unsigned NewOpc = 0;
2423         if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc,
2429           const MCInstrDesc &MCID = TII->get(NewOpc);