Searched defs:NewN1 (Results 1 – 6 of 6) sorted by relevance
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 5048 SDValue NewN1 = CmpZero ? DAG.getConstant(0, dl, OpVT) : LoBits; SimplifySetCC() local
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| H A D | DAGCombiner.cpp | 18220 if (SDValue NewN1 = rebuildSetCC(N1)) visitBRCOND() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 42168 SDValue NewN1 = SimplifyMultipleUseDemandedVectorElts(N1, DemandedRHS, SimplifyDemandedVectorEltsForTargetNode() local
42205 SDValue NewN1 = SimplifyMultipleUseDemandedVectorElts(N1, DemandedRHS, SimplifyDemandedVectorEltsForTargetNode() local
47491 SDValue NewN1 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N1); reduceVMULWidth() local
49927 SDValue NewN1 = TLI.SimplifyMultipleUseDemandedBits(N1, Bits1, Elts1, DAG); combineAnd() local
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 13725 SDValue NewN1 = DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV.getOperand(0), combineOrOfCZERO() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 14714 SDValue NewN1 = DAG.getLogicalNOT(DL, N1, VT); PerformORCombine_i1() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 18020 SDValue NewN1 = DAG.getNode(N->getOperand(1).getOpcode(), DL, HalfVT, N1); performVectorExtCombine() local
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